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| Preface The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core, with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is compatible with the H8/300 CPU. The H8/3937 Series and H8/3937R Series include, a FLEXTM decoder*, five kinds of timers, a 2channel serial communication interface, and an A/D converter, as on-chip peripheral functions necessary for system configuration. The configuration of these series makes them ideal for use as embedded microcomputers in pagers using the FLEXTM decoder system. The H8/3937 Series supports non-roaming, while the H8/3937R Series supports roaming. This manual describes the hardware of the H8/3937 Series and H8/3937R Series. For details on H8/3937 Series and 3937R Series instruction set, refer to the H8/300L Series Programming Manual. Note: * FLEX is a trademark of Motorola Inc. Contents Section 1 1.1 1.2 1.3 Overview............................................................................................................ Overview ............................................................................................................................ Internal Block Diagram ...................................................................................................... Pin Arrangement and Functions......................................................................................... 1.3.1 Pin Arrangement ................................................................................................... 1.3.2 Pin Functions......................................................................................................... 1 1 5 6 6 7 Section 2 2.1 CPU ..................................................................................................................... 13 13 13 14 14 15 15 15 16 17 18 19 20 20 22 26 28 30 31 31 33 37 39 40 42 42 43 45 45 46 46 46 i 2.2 2.3 2.4 2.5 2.6 2.7 Overview ............................................................................................................................ 2.1.1 Features ................................................................................................................. 2.1.2 Address Space....................................................................................................... 2.1.3 Register Configuration .......................................................................................... Register Descriptions ......................................................................................................... 2.2.1 General Registers .................................................................................................. 2.2.2 Control Registers................................................................................................... 2.2.3 Initial Register Values........................................................................................... Data Formats ...................................................................................................................... 2.3.1 Data Formats in General Registers ....................................................................... 2.3.2 Memory Data Formats .......................................................................................... Addressing Modes.............................................................................................................. 2.4.1 Addressing Modes................................................................................................. 2.4.2 Effective Address Calculation............................................................................... Instruction Set .................................................................................................................... 2.5.1 Data Transfer Instructions..................................................................................... 2.5.2 Arithmetic Operations........................................................................................... 2.5.3 Logic Operations................................................................................................... 2.5.4 Shift Operations .................................................................................................... 2.5.5 Bit Manipulations.................................................................................................. 2.5.6 Branching Instructions .......................................................................................... 2.5.7 System Control Instructions.................................................................................. 2.5.8 Block Data Transfer Instruction............................................................................ Basic Operational Timing .................................................................................................. 2.6.1 Access to On-Chip Memory (RAM, ROM) ......................................................... 2.6.2 Access to On-Chip Peripheral Modules................................................................ CPU States ......................................................................................................................... 2.7.1 Overview............................................................................................................... 2.7.2 Program Execution State....................................................................................... 2.7.3 Program Halt State ................................................................................................ 2.7.4 Exception-Handling State ..................................................................................... 2.8 2.9 Memory Map...................................................................................................................... Application Notes............................................................................................................... 2.9.1 Notes on Data Access ........................................................................................... 2.9.2 Notes on Bit Manipulation .................................................................................... 2.9.3 Notes on Use of the EEPMOV Instruction ........................................................... 47 50 50 52 58 Section 3 3.1 3.2 Exception Handling ........................................................................................ 59 59 59 59 59 60 61 61 63 72 73 74 79 80 80 81 83 85 85 85 85 86 89 91 92 92 94 3.3 3.4 Overview ............................................................................................................................ Reset................................................................................................................................... 3.2.1 Overview............................................................................................................... 3.2.2 Reset Sequence ..................................................................................................... 3.2.3 Interrupt Immediately after Reset ......................................................................... Interrupts ............................................................................................................................ 3.3.1 Overview............................................................................................................... 3.3.2 Interrupt Control Registers ................................................................................... 3.3.3 External Interrupts................................................................................................. 3.3.4 Internal Interrupts.................................................................................................. 3.3.5 Interrupt Operations .............................................................................................. 3.3.6 Interrupt Response Time....................................................................................... Application Notes............................................................................................................... 3.4.1 Notes on Stack Area Use ...................................................................................... 3.4.2 Notes on Rewriting Port Mode Registers ............................................................. 3.4.3 Notes on Interrupt Request Flag Clearing Methods ............................................. Section 4 4.1 4.2 4.3 4.4 4.5 Clock Pulse Generators ................................................................................. Overview ............................................................................................................................ 4.1.1 Block Diagram ...................................................................................................... 4.1.2 System Clock and Subclock.................................................................................. System Clock Generator .................................................................................................... Subclock Generator ............................................................................................................ Prescalers ........................................................................................................................... Note on Oscillators............................................................................................................. 4.5.1 Definition of Oscillation Settling Standby Time .................................................. 4.5.2 Notes on Use of Crystal Oscillator Element (Excluding Ceramic Oscillator Element) .............................................................. Section 5 5.1 5.2 Power-Down Modes....................................................................................... 95 Overview ............................................................................................................................ 95 5.1.1 System Control Registers...................................................................................... 98 Sleep Mode......................................................................................................................... 103 5.2.1 Transition to Sleep Mode ...................................................................................... 103 5.2.2 Clearing Sleep Mode............................................................................................. 103 5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode............................................... 104 ii 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Standby Mode..................................................................................................................... 105 5.3.1 Transition to Standby Mode.................................................................................. 105 5.3.2 Clearing Standby Mode ........................................................................................ 105 5.3.3 Oscillator Settling Time after Standby Mode is Cleared ...................................... 105 5.3.4 Standby Mode Transition and Pin States .............................................................. 106 5.3.5 Notes on External Input Signal Changes before/after Standby Mode .................. 107 Watch Mode ....................................................................................................................... 109 5.4.1 Transition to Watch Mode .................................................................................... 109 5.4.2 Clearing Watch Mode ........................................................................................... 109 5.4.3 Oscillator Settling Time after Watch Mode is Cleared......................................... 109 5.4.4 Notes on External Input Signal Changes before/after Watch Mode..................... 109 Subsleep Mode ................................................................................................................... 110 5.5.1 Transition to Subsleep Mode ................................................................................ 110 5.5.2 Clearing Subsleep Mode ....................................................................................... 110 Subactive Mode.................................................................................................................. 111 5.6.1 Transition to Subactive Mode............................................................................... 111 5.6.2 Clearing Subactive Mode...................................................................................... 111 5.6.3 Operating Frequency in Subactive Mode ............................................................. 111 Active (Medium-Speed) Mode........................................................................................... 112 5.7.1 Transition to Active (Medium-Speed) Mode........................................................ 112 5.7.2 Clearing Active (Medium-Speed) Mode............................................................... 112 5.7.3 Operating Frequency in Active (Medium-Speed) Mode ...................................... 112 Direct Transfer ................................................................................................................... 113 5.8.1 Overview of Direct Transfer................................................................................. 113 5.8.2 Direct Transition Times ........................................................................................ 114 5.8.3 Notes on External Input Signal Changes before/after Direct Transition .............. 116 Module Standby Mode....................................................................................................... 117 5.9.1 Setting Module Standby Mode ............................................................................. 117 5.9.2 Clearing Module Standby Mode........................................................................... 117 Section 6 6.1 6.2 ROM.................................................................................................................... 119 6.3 6.4 Overview ............................................................................................................................ 119 6.1.1 Block Diagram ...................................................................................................... 119 PROM Mode ...................................................................................................................... 120 6.2.1 Setting to PROM Mode......................................................................................... 120 6.2.2 Socket Adapter Pin Arrangement and Memory Map ........................................... 120 Programming...................................................................................................................... 123 6.3.1 Writing and Verifying........................................................................................... 123 6.3.2 Programming Precautions..................................................................................... 128 Reliability of Programmed Data ........................................................................................ 129 Section 7 7.1 RAM.................................................................................................................... 131 Overview ............................................................................................................................ 131 iii 7.1.1 Block Diagram ...................................................................................................... 131 Section 8 8.1 8.2 I/O Ports ............................................................................................................. 133 8.3 8.4 8.5 8.6 8.7 8.8 Overview ............................................................................................................................ 133 Port 1 .................................................................................................................................. 135 8.2.1 Overview............................................................................................................... 135 8.2.2 Register Configuration and Description ............................................................... 135 8.2.3 Pin Functions......................................................................................................... 140 8.2.4 Pin States............................................................................................................... 142 8.2.5 MOS Input Pull-Up............................................................................................... 142 Port 2 [Chip Internal I/O Port] ........................................................................................... 143 8.3.1 Overview............................................................................................................... 143 8.3.2 Register Configuration and Description ............................................................... 143 8.3.3 Function ................................................................................................................ 147 8.3.4 States ..................................................................................................................... 147 Port 3 .................................................................................................................................. 148 8.4.1 Overview............................................................................................................... 148 8.4.2 Register Configuration and Description ............................................................... 148 8.4.3 Pin Functions......................................................................................................... 151 8.4.4 Pin States............................................................................................................... 153 8.4.5 MOS Input Pull-Up............................................................................................... 153 Port 4* ................................................................................................................................ 154 8.5.1 Overview............................................................................................................... 154 8.5.2 Register Configuration and Description ............................................................... 154 8.5.3 Pin Functions......................................................................................................... 156 8.5.4 Pin States............................................................................................................... 157 Port 5 .................................................................................................................................. 158 8.6.1 Overview............................................................................................................... 158 8.6.2 Register Configuration and Description ............................................................... 158 8.6.3 Pin Functions......................................................................................................... 160 8.6.4 Pin States............................................................................................................... 161 8.6.5 MOS Input Pull-Up............................................................................................... 161 Port 6 .................................................................................................................................. 162 8.7.1 Overview............................................................................................................... 162 8.7.2 Register Configuration and Description ............................................................... 162 8.7.3 Pin Functions......................................................................................................... 164 8.7.4 Pin States............................................................................................................... 164 8.7.5 MOS Input Pull-Up............................................................................................... 164 Port 7 .................................................................................................................................. 165 8.8.1 Overview............................................................................................................... 165 8.8.2 Register Configuration and Description ............................................................... 165 8.8.3 Pin Functions......................................................................................................... 167 8.8.4 Pin States............................................................................................................... 167 iv 8.9 8.10 8.11 8.12 8.13 8.14 Port 8 .................................................................................................................................. 168 8.9.1 Overview............................................................................................................... 168 8.9.2 Register Configuration and Description ............................................................... 168 8.9.3 Pin Functions......................................................................................................... 169 8.9.4 Pin States............................................................................................................... 169 Port 9 .................................................................................................................................. 170 8.10.1 Overview............................................................................................................... 170 8.10.2 Register Configuration and Description ............................................................... 170 8.10.3 Pin Functions......................................................................................................... 172 8.10.4 Pin States............................................................................................................... 172 Port A ................................................................................................................................. 173 8.11.1 Overview............................................................................................................... 173 8.11.2 Register Configuration and Description ............................................................... 173 8.11.4 Pin States............................................................................................................... 174 Port B ................................................................................................................................. 175 8.12.1 Overview............................................................................................................... 175 8.12.2 Register Configuration and Description ............................................................... 175 Input/Output Data Inversion Function ............................................................................... 176 8.13.1 Overview............................................................................................................... 176 8.13.2 Register Configuration and Descriptions .............................................................. 176 8.13.3 Note on Modification of Serial Port Control Register .......................................... 178 Application Note ................................................................................................................ 178 8.14.1 The Management of the Un-Use Terminal ........................................................... 178 Section 9 9.1 9.2 9.3 9.4 Timers................................................................................................................. 179 Overview ............................................................................................................................ 179 Timer A .............................................................................................................................. 180 9.2.1 Overview............................................................................................................... 180 9.2.2 Register Descriptions ............................................................................................ 182 9.2.3 Timer Operation .................................................................................................... 186 9.2.4 Timer A Operation States ..................................................................................... 187 9.2.5 Application Note................................................................................................... 187 Timer C .............................................................................................................................. 188 9.3.1 Overview............................................................................................................... 188 9.3.2 Register Descriptions ............................................................................................ 190 9.3.3 Timer Operation .................................................................................................... 193 9.3.4 Timer C Operation States...................................................................................... 195 Timer F............................................................................................................................... 196 9.4.1 Overview............................................................................................................... 196 9.4.2 Register Descriptions ............................................................................................ 199 9.4.3 CPU Interface........................................................................................................ 206 9.4.4 Operation............................................................................................................... 209 9.4.5 Application Notes ................................................................................................. 212 v 9.5 9.6 Timer G .............................................................................................................................. 215 9.5.1 Overview............................................................................................................... 215 9.5.2 Register Descriptions ............................................................................................ 217 9.5.3 Noise Canceler ...................................................................................................... 221 9.5.4 Operation............................................................................................................... 223 9.5.5 Application Notes ................................................................................................. 227 9.5.6 Timer G Application Example .............................................................................. 232 Watchdog Timer................................................................................................................. 233 9.6.1 Overview............................................................................................................... 233 9.6.2 Register Descriptions ............................................................................................ 234 9.6.3 Timer Operation .................................................................................................... 238 9.6.4 Watchdog Timer Operation States ........................................................................ 239 Section 10 Serial Communication Interface................................................................. 241 10.1 Overview ............................................................................................................................ 10.2 SCI1 [Chip Internal Function] ........................................................................................... 10.2.1 Overview............................................................................................................... 10.2.2 Register Descriptions ............................................................................................ 10.2.3 Operation............................................................................................................... 10.2.4 Interrupt Source..................................................................................................... 10.2.5 Application Note................................................................................................... 10.3 SCI3 ................................................................................................................................... 10.3.1 Overview............................................................................................................... 10.3.2 Register Descriptions ............................................................................................ 10.3.3 Operation............................................................................................................... 10.3.4 Interrupts ............................................................................................................... 10.3.5 Application Notes ................................................................................................. 241 242 242 244 250 252 253 254 254 258 280 308 309 Section 11 A/D Converter .................................................................................................. 315 11.1 Overview ............................................................................................................................ 315 11.1.1 Features ................................................................................................................. 315 11.1.2 Block Diagram ...................................................................................................... 316 11.1.3 Pin Configuration .................................................................................................. 317 11.1.4 Register Configuration .......................................................................................... 317 11.2 Register Descriptions ......................................................................................................... 318 11.2.1 A/D Result Registers (ADRRH, ADRRL) ........................................................... 318 11.2.2 A/D Mode Register (AMR) .................................................................................. 318 11.2.3 A/D Start Register (ADSR)................................................................................... 320 11.2.4 Clock Stop Register 1 (CKSTPR1)....................................................................... 321 11.3 Operation ............................................................................................................................ 322 11.3.1 A/D Conversion Operation ................................................................................... 322 11.3.2 Start of A/D Conversion by External Trigger Input ............................................. 322 11.3.3 A/D Converter Operation Modes .......................................................................... 323 vi 11.4 Interrupts ............................................................................................................................ 323 11.5 Typical Use ........................................................................................................................ 323 11.6 Application Notes............................................................................................................... 327 Section 12 FLEXTM Roaming Decoder II ..................................................................... 329 12.1 Overview ............................................................................................................................ 329 12.1.1 Features ................................................................................................................. 329 12.1.2 System Block Diagram ......................................................................................... 330 12.1.3 Functional Block Diagram .................................................................................... 332 12.2 SPI Packets............................................................................................................................ 333 12.2.1 Packet Communication Initiated by the Host ....................................................... 333 12.2.2 Packet Communication Initiated by the FLEX decoder ....................................... 334 12.2.3 Host-to-Decoder Packet Map................................................................................ 336 12.2.4 Decoder-to-Host Packet Map................................................................................ 338 12.3 Host-to-Decoder Packet Descriptions ................................................................................ 338 12.3.1 Checksum Packet .................................................................................................. 338 12.3.2 Configuration Packet............................................................................................. 341 12.3.3 Control Packet....................................................................................................... 344 12.3.4 All Frame Mode Packet ........................................................................................ 345 12.3.5 Operator Messaging Address Enable Packet ........................................................ 347 12.3.6 Roaming Control Packet ....................................................................................... 347 12.3.7 Timing Control Packet .......................................................................................... 350 12.3.8 Receiver Line Control Packet ............................................................................... 351 12.3.9 Receiver Control Configuration Packets............................................................... 351 12.3.10 Frame Assignment Packets ................................................................................... 355 12.3.11 User Address Enable Packet ................................................................................. 356 12.3.12 User Address Assignment Packets........................................................................ 357 12.4 Decoder-to-Host Packet Descriptions ................................................................................ 358 12.4.1 Block Information Word Packet ........................................................................... 359 12.4.2 Address Packet ...................................................................................................... 360 12.4.3 Vector Packet ........................................................................................................ 361 12.4.4 Message Packet..................................................................................................... 366 12.4.5 Roaming Status Packet ......................................................................................... 366 12.4.6 Receiver Shutdown Packet ................................................................................... 369 12.4.7 Status Packet ......................................................................................................... 370 12.4.8 Part ID Packet ....................................................................................................... 372 12.5 Application Notes............................................................................................................... 374 12.5.1 Receiver Control ................................................................................................... 374 12.5.2 Message Building.................................................................................................. 377 12.5.3 Building a Fragmented Message........................................................................... 379 12.5.4 Operation of a Temporary Address....................................................................... 382 12.5.5 Using the Receiver Shutdown Packet ................................................................... 384 12.6 Timing Diagrams (Reference Data) ................................................................................... 387 vii 12.6.1 SPI Timing ............................................................................................................ 387 12.6.2 Start-up Timing..................................................................................................... 389 12.6.3 Reset Timing......................................................................................................... 390 Section 13 Electrical Characteristics............................................................................... 391 13.1 Absolute Maximum Ratings............................................................................................... 391 13.2 Electrical Characteristics.................................................................................................... 392 13.2.1 Power Supply Voltage and Operating Range ....................................................... 392 13.2.2 DC Characteristics ................................................................................................ 394 13.2.3 AC Characteristics ................................................................................................ 398 13.2.4 A/D Converter Characteristics .............................................................................. 401 13.3 Operation Timing ............................................................................................................... 402 13.4 Output Load Circuit ........................................................................................................... 405 13.5 Resonator Equivalent Circuit ............................................................................................. 405 13.6 Usage Note ......................................................................................................................... 406 Appendix A CPU Instruction Set..................................................................................... 407 A.1 A.2 A.3 Instructions......................................................................................................................... 407 Operation Code Map .......................................................................................................... 415 Number of Execution States............................................................................................... 417 Appendix B Internal I/O Registers .................................................................................. 423 B.1 B.2 Addresses ........................................................................................................................... 423 Functions ............................................................................................................................ 426 Appendix C I/O Port Block Diagrams ........................................................................... 478 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.11 Block Diagrams of Port 1................................................................................................... 478 Block Diagrams of Port 2 [Chip Internal I/O Port] ............................................................ 482 Block Diagrams of Port 3................................................................................................... 486 Block Diagrams of Port 4................................................................................................... 493 Block Diagram of Port 5 .................................................................................................... 497 Block Diagram of Port 6 .................................................................................................... 498 Block Diagram of Port 7 .................................................................................................... 499 Block Diagrams of Port 8................................................................................................... 500 Block Diagram of Port 9 .................................................................................................... 501 Block Diagram of Port A ................................................................................................... 502 Block Diagram of Port B ................................................................................................... 503 Appendix D Port States in the Different Processing States ..................................... 504 Appendix E List of Product Codes .................................................................................. 505 Appendix F Package Dimensions .................................................................................... 506 viii Section 1 Overview 1.1 Overview The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. The H8/3937 and H8/3937R Series are H8/300L Series microcomputers with an on-chip FLEXTM decoder. With on-chip peripheral functions including a FLEXTM decoder, five kinds of timers, a 2-channel serial communication interface, and an A/D converter, the configuration of these series makes them ideal for use as embedded microcomputers in pagers using the FLEXTM system, which require low power consumption. Models in the H8/3937 Series and H8/3937R Series are the H8/3935 and H8/3935R, with on-chip 40-kbyte ROM and 2-kbyte RAM, the H8/3936 and H8/3936R, with on-chip 48-kbyte ROM and 2-kbyte RAM, and the H8/3937 and H8/3937R, with on-chip 60-kbyte ROM and 2-kbyte RAM. The H8/3937 and H8/3937R Series are also available in a ZTATTM* version with on-chip PROM which can be programmed as required by the user. The H8/3937 Series supports non-roaming, while the H8/3937R Series supports roaming. Table 1-1 summarizes the features of the H8/3937 Series and H8/3937R Series. Note: * ZTAT (Zero Turn Around Time) is a trademark of Hitachi, Ltd. 1 Table 1-1 Item CPU Features Description High-speed H8/300L CPU * General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) * Operating speed Max. operating speed: 5 MHz Add/subtract: 0.4 s (operating at 5 MHz) Multiply/divide: 2.8 s (operating at 5 MHz) Can run on 76.8 kHz or 160 kHz subclock * Instruction set compatible with H8/300 CPU Instruction length of 2 bytes or 4 bytes Basic arithmetic operations between registers MOV instruction for data transfer between memory and registers * Typical instructions Multiply (8 bits x 8 bits) Divide (16 bits / 8 bits) Bit accumulator Register-indirect designation of bit position Interrupts 36 interrupt sources * * * 12 external interrupt sources (IRQ4 to IRQ1, WKP7 to WKP0) 23 internal interrupt sources 1 internal IRQ0 interrupt source (IRQ0) Clock pulse generators Two on-chip clock pulse generators * * System clock pulse generator: 2 to 10 MHz Subclock pulse generator: 160 kHz, 76.8 kHz Power-down modes Seven power-down modes * * * * * * * Sleep (high-speed) mode Sleep (medium-speed) mode Standby mode Watch mode Subsleep mode Subactive mode Active (medium-speed) mode 2 Item Memory Description Large on-chip memory * * * H8/3935, H8/3935R: 40-kbyte ROM, 2-kbyte RAM H8/3936, H8/3936R: 48-kbyte ROM, 2-kbyte RAM H8/3937, H8/3937R: 60-kbyte ROM, 2-kbyte RAM I/O ports 67 pins * * * * 59 I/O pins 8 input pins 5 internal I/O 1 internal input Timers Five on-chip timers * Timer A: 8-bit timer Count-up timer with selection of eight internal clock signals divided from the system clock (o)* and four clock signals divided from the watch clock (ow)* Timer C: 8-bit timer Count-up/down timer with selection of seven internal clock signals or event input from external pin Auto-reloading * Timer F: 16-bit timer Can be used as two independent 8-bit timers Count-up timer with selection of four internal clock signals or event input from external pin Provision for toggle output by means of compare-match function * Timer G: 8-bit timer Count-up timer with selection of four internal clock signals Incorporates input capture function (built-in noise canceler) * Watchdog timer Reset signal generated by overflow of 8-bit counter * Serial communication interface Two serial communication interface channels on chip Internal serial communication interface function * SCI1: Synchronous serial interface 8-bit or 16-bit transfer data can be selected Used for interface to on-chip FLEXTM decoder * * SCI31: 8-bit synchronous/asynchronous serial interface Incorporates multiprocessor communication function SCI32: 8-bit synchronous/asynchronous serial interface Incorporates multiprocessor communication function 3 Item A/D converter Description Successive approximations using a resistance ladder * * 8-channel analog input pins Conversion time: 31/o or 62/o per channel FLEXTM decoder II On-chip FLEXTM decoder II * * * Conforms to FLEXTM protocol revision 1.9 Decoding capability: 1600, 3200, 6400 bits/second Decoding phase: Any-phase, single-phase Product lineup Product Code Mask ROM Specification Version Non-roaming HD6433935X HD6433935W HD6433936X HD6433936W HD6433937X HD6433937W Roaming ZTAT Version -- -- -- -- HD6473937X HD6473937W Package ROM/RAM Size (Byte) 100-pin TQFP 40 k/2 k (TFP-100B) 100-pin TQFP (TFP-100G) 100-pin TQFP 48 k/2 k (TFP-100B) 100-pin TQFP (TFP-100G) 100-pin TQFP 60 k/2 k (TFP-100B) 100-pin TQFP (TFP-100G) 100-pin TQFP 40 k/2 k (TFP-100B) 100-pin TQFP (TFP-100G) 100-pin TQFP 48 k/2 k (TFP-100B) 100-pin TQFP (TFP-100G) HD6433935RX -- HD6433935RW -- HD6433936RX -- HD6433936RW -- HD6433937RX HD6473937RX 100-pin TQFP 60 k/2 k (TFP-100B) HD6433937RW HD6473937RW 100-pin TQFP (TFP-100G) Note: * See section 4, Clock Pulse Generator, for the definition of o and ow. 4 1.2 Internal Block Diagram Figure 1-1 shows a block diagram of the H8/3937 Series and H8/3937R Series. RES TEST TEST9H OSC1 OSC2 DX1 DX2 VSS VSS VCC VCC ROM (60 k, 48 k, 40 k) RAM (2 k) P30 P31/UD P32/RESO P33/SCK31 P34/RXD31 P35/TXD31 P36 P37 P50/WKP0 P51/WKP1 P52/WKP2 P53/WKP3 P54/WKP4 P55/WKP5 P56/WKP6 P57/WKP7 Port A P10/TMOW P11/TMOFL P12/TMOFH P13/TMIG P14/IRQ4/ADTRG P15/IRQ1/TMIC P16/IRQ2 P17/IRQ3/TMIF H8/300L CPU TEST20 TEST21 TEST22 TEST23 TEST24 TEST43 PA3 PA2 PA1 PA0 P93 P92 P91 P90 P87 P86 P85 P84 P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65 P64 P63 P62 P61 P60 System clock OSC Port 1 Sub clock OSC Port 3 Timer-A Timer-C Port 5 Timer-F Timer-G Serial communication interface 32 PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 WDT Port B Port 6 Internal I/O port Internal functions Serial communication interface 1 A/D (10-bit) Port 4 Port 2 AVCC AVSS P43/IRQ0 READY FLEXTM decoder Note: Serial communication interface 1, P20 to P24, and P43, are internal functions that perform interfacing to the FLEXTM decoder incorporated in the chip. P40/SCK32 P41/RXD32 P42/TXD32 CLKOUT LOBAT SYMCLK S0/IFIN S1 S2 S3 S4 S5 S6 S7 EXTS0 EXTS1 TESTD Figure 1-1 Block Diagram 5 SCK MISO MOSI SS RESET P20/SCK1 P21/SI1 P22/SO1 P23 P24 Port 7 Port 8 Serial communication interface 31 Port 9 1.3 1.3.1 Pin Arrangement and Functions Pin Arrangement The H8/3937 Series and H8/3937R Series pin arrangement is shown in figure 1-2. P41/RXD32 P40/SCK32 P42/TXD32 SYMCLK TEST24 TEST23 TEST22 TEST21 TEST20 TEST43 LOBAT EXTS0 EXTS1 P77 P76 P75 P74 P73 P72 P71 P70 53 VCC 52 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 S5 S4 S3 S2 S1 S0/IFIN CLKOUT TESTD DX2 DX1 TEST P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 AVCC PB0/AN0 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VSS S6 S7 P67 P66 P65 P64 P63 P62 P61 P60 P57/WKP7 P56/WKP6 P55/WKP5 P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 TESTA9H P37 P36 P35/TXD31 P34/RXD31 P33/SCK31 P32/RESO P31/UD P30 Top View (TFP-100B, TFP-100G) 14/IRQ4/ADTRG P15/IRQ1/TMIC P17/IRQ3/TMIF P11/TMOFL P12/TMOFH P10/TMOW P13/TMIG PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 P16/IRQ2 OSC2 OSC1 AVSS VCC VSS RES PA0 PA1 PA2 Figure 1-2 Pin Arrangement (TFP-100B and TFP-100G: Top View) 6 PA3 1.3.2 Pin Functions Table 1-2 outlines the pin functions of the H8/3937 Series and H8/3937R Series. Table 1-2 Pin Functions Pin No. Type Power source pins Symbol VCC VSS AVCC TFP-100B TFP-100G 12 52 11 51 99 I/O Input Input Input Name and Functions Power supply: All VCC pins should be connected to the system power supply. Ground: All VSS pins should be connected to the system power supply (0 V). Analog power supply: This is the power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply. Analog ground: This is the A/D converter ground pin. It should be connected to the system power supply (0V). These pins connect to a crystal or ceramic oscillator, or can be used to input an external clock. See section 4, Clock Pulse Generators, for a typical connection diagram. These pins connect to a 76.8-kHz or 160-kHz crystal oscillator. Output See section 4, Clock Pulse Generators, for a typical connection diagram. Reset: When this pin is driven low, the chip is reset Reset output: Outputs the CPU internal reset signal. Test pins: These pins are reserved and cannot be used. They should be connected to VSS . Test pins: These pins are reserved and cannot be used. They should be left open. AVSS 8 Input Clock pins OSC 1 OSC 2 10 9 Input Output DX 1 DX 2 85 84 Input System control RES RESO TEST TESTD TESTA9H TEST20 to TEST24 TEST43 13 28 86 83 34 65 to 69 64 Input Output Input Output 7 Pin No. Type Interrupt pins Symbol IRQ1 IRQ2 IRQ3 IRQ4 WKP 7 to WKP 0 Internal IRQ 0 IRQ0 interrupt pin TFP-100B TFP-100G 19 20 21 18 42 to 35 I/O Input Name and Functions IRQ interrupt request 0 and 1: These are input pins for edge-sensitive external interrupts, with a selection of rising or falling edge. Wakeup interrupt request 0 to 7: These are input pins for rising or falling- edgesensitive external interrupts. Internal interrupt request 0: This is the request pin for an edge-sensistive internal interrupt, with a selection of rising or falling edge. Clock output: This is an output pin for waveforms generated by the timer A output circuit. Timer C event input: This is an event input pin for input to the timer C counter. Timer C up/down select: This pin selects up- or down-counting for the timer C counter. The counter operates as a downcounter when this pin is high, and as an upcounter when low. Timer F event input: This is an event input pin for input to the timer F counter. Timer FL output: This is an output pin for waveforms generated by the timer FL output compare function. Timer FH output: This is an output pin for waveforms generated by the timer FH output compare function. Timer G capture input: This is an input pin for timer G input capture. Port B: This is an 8-bit input port. Port 4 (bits 2 to 0): This is a 3-bit I/O port. Input or output can be designated for each bit by means of port control register 4 (PCR4). Input - Input Timer pins TMOW 14 Output TMIC UD 19 27 Input Input TMIF TMOFL 21 15 Input Output TMOFH 16 Output TMIG I/O ports PB7 to PB 0 P42 to P4 0 17 7 to 1, 100 63 to 61 Input Input I/O 8 Pin No. Type I/O ports Symbol PA3 to PA 0 TFP-100B TFP-100G 25 to 22 I/O I/O Name and Functions Port A: This is a 4-bit I/O port. Input or output can be designated for each bit by means of port control register A (PCRA). Port 1: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 1 (PCR1). Port 3: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 3 (PCR3). Port 5: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 5 (PCR5). Port 6: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 6 (PCR6). Port 7: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 7 (PCR7). Port 8: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 8 (PCR8). Port 9: This is a 4-bit I/O port. Input or output can be designated for each bit by means of port control register 9 (PCR9). Port 4 (bit 3): This is an internal 1-bit input port. Port 2: This is an internal 5-bit I/O port. Input or output can be designated for each bit by means of port control register 2 (PCR2). SCI31 receive data input: This is the SCI31 data input pin. SCI31 transmit data output: This is the SCI31 data output pin. SCI31 clock I/O: This is the SCI31 clock I/O pin. P17 to P1 0 21 to 14 I/O P37 to P3 0 33 to 26 I/O P57 to P5 0 42 to 35 I/O P67 to P6 0 50 to 43 I/O P77 to P7 0 60 to 53 I/O P87 to P8 0 94 to 87 I/O P93 to P9 0 98 to 95 I/O Internal I/O ports P43 P24 to P2 0 - - Input I/O Serial communication interface (SCI) RXD31 TXD31 SCK 31 30 31 29 Input Output I/O 9 Pin No. Type Serial communication interface (SCI) Symbol RXD32 TXD32 SCK 32 TFP-100B TFP-100G 62 63 61 - - - 7 to 1, 100 I/O Input Output I/O Input Output I/O Input Name and Functions SCI32 receive data input: This is the SCI32 data input pin. SCI32 transmit data output: This is the SCI32 data output pin. SCI32 clock I/O: This is the SCI32 clock I/O pin. SCI1 receive data input: This is the SCI1 data input pin. SCI1 transmit data output: This is the SCI1 data output pin SCI1 clock I/O: This is the SCI1 clock I/O pin. Analog input channels 7 to 0: These are analog data input channels to the A/D converter A/D converter trigger input: This is the external trigger input pin to the A/D converter Decoder reset: A reset is executed when this pin goes low. Decode symbol input: MSb of the symbol currently being decoded. Decode symbol input: LSb of the symbol currently being decoded. Voltage drop detection input: Input pin for the voltage drop detection signal. SPI mode select: Slave mode is selected when this pin goes low. SPI clock input: SPI clock input. SPI receive data input: SPI data input. SPI transmit data output: SPI data output. Ready pin: Goes low when the SPI is ready to transmit/receive. Internal serial SI 1 communication SO1 interface (SCI) SCK 1 A/D converter AN 7 to AN0 ADTRG 18 Input FLEXTM decoder II RESET EXTS1 EXTS0 LOBAT SS SCK MOSI MISO READY - 71 72 70 - - - - - Input Input Input Input Input Input Input Output Output 10 Pin No. Type FLEXTM decoder II Symbol CLKOUT TFP-100B TFP-100G 82 I/O Output Name and Functions Clock output: 38.4 kHz or 40 kHz clock output (derived from on-chip crystal oscillator). Symbol clock output: Recovered symbol clock pin. Receiver control output: Receiver control signal output pin (when using external demodulator). Receiver control output: Three-state receiver control signal output. IF signal input: Limited IF signal input pin (when using internal demodulator). SYMCLK S0 73 81 Output Output S1 to S7 IFIN 80 to 74 81 Output Input 11 12 Section 2 CPU 2.1 Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. * General-register architecture Sixteen 8-bit general registers, also usable as eight 16-bit general registers * Instruction set with 55 basic instructions, including: Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct Register indirect Register indirect with displacement Register indirect with post-increment or pre-decrement Absolute address Immediate Program-counter relative Memory indirect * 64-kbyte address space * High-speed operation All frequently used instructions are executed in two to four states High-speed arithmetic and logic operations 8- or 16-bit register-register add or subtract: 0.4 s* 8 x 8-bit multiply: 2.8 s* 16 / 8-bit divide: 2.8 s* * Low-power operation modes SLEEP instruction for transfer to low-power operation Note: * These values are at o = 5 MHz. 13 2.1.2 Address Space The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and data. See 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2-1 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers. General registers (Rn) 7 R0H R1H R2H R3H R4H R5H R6H R7H (SP) 07 R0L R1L R2L R3L R4L R5L R6L R7L SP: Stack pointer 0 Control registers (CR) 15 PC 76543210 I UHUNZVC 0 PC: Program counter CCR: Condition code register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask bit User bit User bit CCR Figure 2-1 CPU Registers 14 2.2 2.2.1 Register Descriptions General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). R7 also functions as the stack pointer (SP), used implicitly by hardware in exception processing and subroutine calls. When it functions as the stack pointer, as indicated in figure 2-2, SP (R7) points to the top of the stack. Lower address side [H'0000] Unused area SP (R7) Stack area Upper address side [H'FFFF] Figure 2-2 Stack Pointer 2.2.2 Control Registers The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR). Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. All instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the PC is ignored (always regarded as 0). Condition Code Register (CCR): This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC, ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for conditional branching (Bcc) instructions. 15 Bit 7--Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1 automatically at the start of exception handling. The interrupt mask bit may be read and written by software. For further details, see section 3.3, Interrupts. Bit 6--User Bit (U): Can be used freely by the user. Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise. The H flag is used implicitly by the DAA and DAS instructions. When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise. Bit 4--User Bit (U): Can be used freely by the user. Bit 3--Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an instruction. Bit 2--Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero result. Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift and rotate instructions, to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. Refer to the H8/300L Series Programming Manual for the action of each instruction on the flag bits. 2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer should be initialized by software, by the first instruction executed after a reset. 16 2.3 Data Formats The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. * Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n = 0, 1, 2, ..., 7). * All arithmetic and logic instructions except ADDS and SUBS can operate on byte data. * The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions operate on word data. * The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in packed BCD form. Each nibble of the byte is treated as a decimal digit. 17 2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2-3. Data Type Register No. 7 Data Format 0 1-bit data RnH 7 6 5 4 3 2 1 0 don't care 7 0 1-bit data RnL don't care 7 6 5 4 3 2 1 0 7 0 LSB Byte data RnH MSB don't care 7 0 LSB Byte data RnL don't care MSB 15 0 LSB Word data Rn MSB 7 4 Upper digit 3 Lower digit 0 4-bit BCD data RnH don't care 7 4 Upper digit 3 Lower digit 0 4-bit BCD data RnL don't care Notation: RnH: Upper byte of general register RnL: Lower byte of general register MSB: Most significant bit LSB: Least significant bit Figure 2-3 Register Data Formats 18 2.3.2 Memory Data Formats Figure 2-4 indicates the data formats in memory. The H8/300L CPU can access word data stored in memory (MOV.W instruction), but the word data must always begin at an even address. If word data starting at an odd address is accessed, the least significant bit of the address is regarded as 0, and the word data starting at the preceding address is accessed. The same applies to instruction codes. Data Type Address Data Format 7 0 1-bit data Byte data Address n Address n Even address Odd address Even address Odd address Even address Odd address 7 MSB 6 5 4 3 2 1 0 LSB Word data MSB Upper 8 bits Lower 8 bits LSB Byte data (CCR) on stack MSB MSB CCR CCR* LSB LSB Word data on stack MSB LSB CCR: Condition code register Note: * Ignored on return Figure 2-4 Memory Data Formats When the stack is accessed using R7 as an address register, word access should always be performed. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to make a complete word. When they are restored, the lower byte is ignored. 19 2.4 2.4.1 Addressing Modes Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2-1. Each instruction uses a subset of these addressing modes. Table 2-1 No. 1 2 3 4 Addressing Modes Address Modes Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Symbol Rn @Rn @(d:16, Rn) @Rn+ @-Rn @aa:8 or @aa:16 #xx:8 or #xx:16 @(d:8, PC) @@aa:8 5 6 7 8 Absolute address Immediate Program-counter relative Memory indirect 1. Register Direct--Rn: The register field of the instruction specifies an 8- or 16-bit general register containing the operand. Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions have 16-bit operands. 2. Register Indirect--@Rn: The register field of the instruction specifies a 16-bit general register containing the address of the operand in memory. 3. Register Indirect with Displacement--@(d:16, Rn): The instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register to obtain the operand address in memory. This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address must be even. 4. Register Indirect with Post-Increment or Pre-Decrement--@Rn+ or @-Rn: * Register indirect with post-increment--@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. 20 The register field of the instruction specifies a 16-bit general register containing the address of the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. * Register indirect with pre-decrement--@-Rn The @-Rn mode is used with MOV instructions that store register contents to memory. The register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. The register retains the decremented value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the register must be even. 5. Absolute Address--@aa:8 or @aa:16: The instruction specifies the absolute address of the operand in memory. The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses. For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is H'FF00 to H'FFFF (65280 to 65535). 6. Immediate--#xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values. The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. 7. Program-Counter Relative--@(d:8, PC): This mode is used in the Bcc and BSR instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. The possible branching range is -126 to +128 bytes (-63 to +64 words) from the current address. The displacement should be an even number. 8. Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. The word located at this address contains the branch destination address. The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the address area is also used as a vector area. See 3.3, Interrupts, for details on the vector area. 21 If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. See 2.3.2, Memory Data Formats, for further information. 2.4.2 Effective Address Calculation Table 2-2 shows how effective addresses are calculated in each of the addressing modes. Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX, CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6). Data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). Bit manipulation instructions can use register direct (1), register indirect (2), or 8-bit absolute addressing (5) to specify the operand. Register indirect (1) (BSET, BCLR, BNOT, and BTST instructions) or 3-bit immediate addressing (6) can be used independently to specify a bit position in the operand. 22 No. 3 0 3 0 Addressing Mode and Instruction Format Effective Address Calculation Method rm 43 0 Effective Address (EA) rn Table 2-2 1 Register direct, Rn 15 87 op 15 0 rm Contents (16 bits) of register indicated by rm 15 43 0 rn Operand is contents of registers indicated by rm/rn 0 2 Register indirect, @Rn 15 76 op 15 0 rm 3 Contents (16 bits) of register indicated by rm 15 43 0 Register indirect with displacement, @(d:16, Rn) rm disp 0 Effective Address Calculation 15 76 op disp 15 0 15 0 4 Contents (16 bits) of register indicated by rm 43 0 Register indirect with post-increment, @Rn+ rm 15 76 op 15 1 or 2 0 Register indirect with pre-decrement, @-Rn 43 0 Contents (16 bits) of register indicated by rm 15 0 15 76 op rm Incremented or decremented by 1 if operand is byte size, 1 or 2 and by 2 if word size 23 24 Effective Address Calculation Method 15 87 No. H'FF 0 Addressing Mode and Instruction Format Effective Address (EA) 5 87 Absolute address @aa:8 abs 15 0 0 15 op @aa:16 op abs 0 15 6 87 0 Immediate #xx:8 IMM Operand is 1- or 2-byte immediate data 0 15 op #xx:16 op IMM 15 0 15 7 Program-counter relative @(d:8, PC) PC contents 15 0 15 87 0 Sign extension disp op disp No. Addressing Mode and Instruction Format Effective Address Calculation Method Effective Address (EA) 8 87 0 Memory indirect, @@aa:8 15 op 15 87 0 abs H'00 15 abs 0 Memory contents (16 bits) Notation: rm, rn: Register field op: Operation field disp: Displacement IMM: Immediate data abs: Absolute address 25 2.5 Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2-3. Table 2-3 Function Data transfer Arithmetic operations Logic operations Shift Bit manipulation Branch System control Block data transfer Instruction Set Instructions MOV, PUSH* , POP* 1 1 Number 1 14 4 8 ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, 14 BXOR, BIXOR, BLD, BILD, BST, BIST Bcc* 2, JMP, BSR, JSR, RTS RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP EEPMOV 5 8 1 Total: 55 Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @-SP. POP Rn is equivalent to MOV.W @SP+, Rn. The same applies to the machine language. 2. Bcc is a conditional branch instruction in which cc represents a condition code. The following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. The notation used is defined next. 26 Notation Rd Rs Rn (EAd), 27 2.5.1 Data Transfer Instructions Table 2-4 describes the data transfer instructions. Figure 2-5 shows their object code formats. Table 2-4 Instruction MOV Data Transfer Instructions Size* B/W Function (EAs) Rd, Rs (Ead) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @-Rn, and @Rn+ addressing modes are available for word data. The @aa:8 addressing mode is available for byte data only. The @-R7 and @R7+ modes require word operands. Do not specify byte size for these two modes. POP W @SP+ Rn Pops a 16-bit general register from the stack. Equivalent to MOV.W @SP+, Rn. PUSH W Rn @-SP Pushes a 16-bit general register onto the stack. Equivalent to MOV.W Rn, @-SP. Notes: * Size: Operand size B: Byte W: Word Certain precautions are required in data access. See 2.9.1, Notes on Data Access, for details. 28 15 8 7 0 MOV RmRn op 15 8 7 rm rn 0 op 15 8 7 rm rn 0 @RmRn op disp 15 8 7 rm rn @(d:16, Rm)Rn 0 op 15 8 7 rm rn 0 @Rm+Rn, or Rn @-Rm op 15 rn 8 7 abs 0 @aa:8Rn op abs 15 8 7 rn @aa:16Rn 0 op 15 rn 8 7 IMM 0 #xx:8Rn op IMM 15 8 7 rn #xx:16Rn 0 op Notation: op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data 1 1 1 rn PUSH, POP @SP+ Rn, or Rn @-SP Figure 2-5 Data Transfer Instruction Codes 29 2.5.2 Arithmetic Operations Table 2-5 describes the arithmetic instructions. Table 2-5 Instruction ADD SUB Arithmetic Instructions Size* B/W Function Rd Rs Rd, Rd + #IMM Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added or subtracted only when both words are in general registers. B Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. B Rd 1 Rd Increments or decrements a general register by 1. W Rd 1 Rd, Rd 2 Rd Adds or subtracts 1 or 2 to or from a general register B Rd decimal adjust Rd Decimal-adjusts (adjusts to 4-bit BCD) an addition or subtraction result in a general register by referring to the CCR B Rd x Rs Rd Performs 8-bit x 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU DIVXU B Rd / Rs Rd Performs 16-bit / 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder CMP B/W Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and indicates the result in the CCR. Word data can be compared only between two general registers. NEG B 0 - Rd Rd Obtains the two's complement (arithmetic complement) of data in a general register Notes: * Size: Operand size B: Byte W: Word 30 2.5.3 Logic Operations Table 2-6 describes the four instructions that perform logic operations. Table 2-6 Instruction AND Logic Operation Instructions Size* B Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data OR B Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data XOR B Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data NOT B ~ Rd Rd Obtains the one's complement (logical complement) of general register contents Notes: * Size: Operand size B: Byte 2.5.4 Shift Operations Table 2-7 describes the eight shift instructions. Table 2-7 Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Shift Instructions Size* B Function Rd shift Rd Performs an arithmetic shift operation on general register contents B Rd shift Rd Performs a logical shift operation on general register contents B Rd rotate Rd Rotates general register contents B Rd rotate through carry Rd Rotates general register contents through the C (carry) bit Notes: * Size: Operand size B: Byte 31 Figure 2-6 shows the instruction code format of arithmetic, logic, and shift instructions. 15 8 7 0 op 15 8 7 rm rn 0 ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT 0 op 15 8 7 rn op 15 8 7 rm rn 0 MULXU, DIVXU op 15 rn 8 7 IMM 0 ADD, ADDX, SUBX, CMP (#XX:8) op 15 8 7 rm rn 0 AND, OR, XOR (Rm) op 15 rn 8 7 IMM 0 AND, OR, XOR (#xx:8) op Notation: Operation field op: rm, rn: Register field IMM: Immediate data rn SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Figure 2-6 Arithmetic, Logic, and Shift Instruction Codes 32 2.5.5 Bit Manipulations Table 2-8 describes the bit-manipulation instructions. Figure 2-7 shows their object code formats. Table 2-8 Instruction BSET Bit-Manipulation Instructions Size* B Function 1 ( BCLR B 0 ( BNOT B ~ ( BTST B ~ ( BAND B C ( BIAND B C [~ ( BOR B BIOR B C [~ ( Notes: * Size: Operand size B: Byte 33 Instruction BXOR Size* B Function C ( BIXOR B C [~( BLD BILD B B BST BIST B B Notes: * Size: Operand size B: Byte Certain precautions are required in bit manipulation. See 2.9.2, Notes on Bit Manipulation, for details. 34 BSET, BCLR, BNOT, BTST 15 8 7 0 op 15 8 7 IMM rn 0 Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm) 0 op 15 8 7 rm rn op op 15 8 7 rn IMM 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit No.: 0 immediate (#xx:3) op op 15 8 7 rn rm 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit No.: 0 register direct (Rm) op op 15 8 7 abs IMM 0 0 0 Operand: absolute (@aa:8) 0 Bit No.: 0 immediate (#xx:3) op op rm abs 0 0 0 Operand: absolute (@aa:8) 0 Bit No.: register direct (Rm) BAND, BOR, BXOR, BLD, BST 15 8 7 0 op 15 8 7 IMM rn 0 Operand: register direct (Rn) Bit No.: immediate (#xx:3) op op 15 8 7 rn IMM 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit No.: 0 immediate (#xx:3) op op IMM abs 0 0 0 Operand: absolute (@aa:8) 0 Bit No.: immediate (#xx:3) Notation: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2-7 Bit Manipulation Instruction Codes 35 BIAND, BIOR, BIXOR, BILD, BIST 15 8 7 0 op 15 8 7 IMM rn 0 Operand: register direct (Rn) Bit No.: immediate (#xx:3) op op 15 8 7 rn IMM 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit No.: 0 immediate (#xx:3) op op IMM abs 0 0 0 Operand: absolute (@aa:8) 0 Bit No.: immediate (#xx:3) Notation: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2-7 Bit Manipulation Instruction Codes (cont) 36 2.5.6 Branching Instructions Table 2-9 describes the branching instructions. Figure 2-8 shows their object code formats. Table 2-9 Instruction Bcc Branching Instructions Size -- Function Branches to the designated address if condition cc is true. The branching conditions are given below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 JMP BSR JSR RTS -- -- -- -- Branches unconditionally to a specified address Branches to a subroutine at a specified address Branches to a subroutine at a specified address Returns from a subroutine 37 15 8 7 0 op 15 cc 8 7 disp 0 Bcc op 15 8 7 rm 0 0 0 0 0 JMP (@Rm) op abs 15 8 7 0 JMP (@aa:16) op 15 8 7 abs 0 JMP (@@aa:8) op 15 8 7 disp 0 BSR op 15 8 7 rm 0 0 0 0 0 JSR (@Rm) op abs 15 8 7 0 JSR (@aa:16) op 15 8 7 abs 0 JSR (@@aa:8) op Notation: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address RTS Figure 2-8 Branching Instruction Codes 38 2.5.7 System Control Instructions Table 2-10 describes the system control instructions. Figure 2-9 shows their object code formats. Table 2-10 System Control Instructions Instruction RTE SLEEP LDC Size* -- -- B Function Returns from an exception-handling routine Causes a transition from active mode to a power-down mode. See section 5, Power-Down Modes, for details. Rs CCR, #IMM CCR Moves immediate data or general register contents to the condition code register STC B CCR Rd Copies the condition code register to a specified general register ANDC B CCR #IMM CCR Logically ANDs the condition code register with immediate data ORC B CCR #IMM CCR Logically ORs the condition code register with immediate data XORC B CCR #IMM CCR Logically exclusive-ORs the condition code register with immediate data NOP -- PC + 2 PC Only increments the program counter Notes: * Size: Operand size B: Byte 39 15 8 7 0 op 15 8 7 0 RTE, SLEEP, NOP op 15 8 7 rn 0 LDC, STC (Rn) op IMM ANDC, ORC, XORC, LDC (#xx:8) Notation: op: Operation field rn: Register field IMM: Immediate data Figure 2-9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2-11 describes the block data transfer instruction. Figure 2-10 shows its object code format. Table 2-11 Block Data Transfer Instruction Instruction EEPMOV Size -- Function If R4L 0 then repeat until else next; Block transfer instruction. Transfers the number of data bytes specified by R4L from locations starting at the address indicated by R5 to locations starting at the address indicated by R6. After the transfer, the next instruction is executed. @R5+ @R6+ R4L - 1 R4L R4L = 0 Certain precautions are required in using the EEPMOV instruction. See 2.9.3, Notes on Use of the EEPMOV Instruction, for details. 40 15 8 7 0 op op Notation: op: Operation field Figure 2-10 Block Data Transfer Instruction Code 41 2.6 Basic Operational Timing CPU operation is synchronized by a system clock (o) or a subclock (oSUB). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of o or oSUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2-11 shows the on-chip memory access cycle. Bus cycle T1 state o or o SUB T2 state Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2-11 On-Chip Memory Access Cycle 42 2.6.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used. Figures 2-12 and 2-13 show the on-chip peripheral module access cycle. Two-state access to on-chip peripheral modules Bus cycle T1 state o or o SUB T2 state Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2-12 On-Chip Peripheral Module Access Cycle (2-State Access) 43 Three-state access to on-chip peripheral modules Bus cycle T1 state o or o SUB T2 state T3 state Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access) Address Read data Write data Figure 2-13 On-Chip Peripheral Module Access Cycle (3-State Access) 44 2.7 2.7.1 CPU States Overview There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. In the program halt state there are a sleep (high-speed or medium-speed) mode, standby mode, watch mode, and sub-sleep mode. These states are shown in figure 2-14. Figure 2-15 shows the state transitions. CPU state Reset state The CPU is initialized Program execution state Active (high speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock Active (medium speed) mode The CPU executes successive program instructions at reduced speed, synchronized by the system clock Subactive mode The CPU executes successive program instructions at reduced speed, synchronized by the subclock Low-power modes Program halt state A state in which some or all of the chip functions are stopped to conserve power Sleep (high-speed) mode Sleep (medium-speed) mode Standby mode Watch mode Subsleep mode Exceptionhandling state A transient state in which the CPU changes the processing flow due to a reset or an interrupt Note: See section 5, Power-Down Modes, for details on the modes and their transitions. Figure 2-14 CPU Operation States 45 Reset cleared Reset state Reset occurs Exception-handling state Reset occurs Reset occurs Interrupt source occurs Interrupt source occurs Exceptionhandling complete Program halt state SLEEP instruction executed Program execution state Figure 2-15 State Transitions 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one subactive mode. Operation is synchronized with the system clock in active mode (high speed and medium speed), and with the subclock in subactive mode. See section 5, Power-Down Modes for details on these modes. 2.7.3 Program Halt State In the program halt state there are five modes: two sleep modes (high speed and medium speed), standby mode, watch mode, and subsleep mode. See section 5, Power-Down Modes for details on these modes. 2.7.4 Exception-Handling State The exception-handling state is a transient state occurring when exception handling is started by a reset or interrupt and the CPU changes its normal processing flow. In exception handling caused by an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack. For details on interrupt handling, see section 3.3, Interrupts. 46 2.8 Memory Map The memory map of the H8/3935 and H8/3935R is shown in figure 2-16 (1), that of the H8/3936 and H8/3936R in figure 2-16 (2), and that of the H8/3937 and H8/3937R in figure 2-16 (3). H'0000 Interrupt vector area H'0029 H'002A 40 kbytes On-chip ROM (40960 bytes) H'9FFF Not used H'F780 On-chip RAM H'FF7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF 2048 bytes Figure 2-16 (1) H8/3935 and H8/3935R Memory Map 47 H'0000 Interrupt vector area H'0029 H'002A 48 kbytes (49152 bytes) On-chip ROM H'BFFF Not used H'F780 On-chip RAM H'FF7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF 2048 bytes Figure 2-16 (2) H8/3936 and H8/3936R Memory Map 48 H'0000 Interrupt vector area H'0029 H'002A 60 kbytes On-chip ROM (60928 bytes) H'EDFF Not used H'F780 On-chip RAM H'FF7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF 2048 bytes Figure 2-16 (3) H8/3937 and H8/3937R Memory Map 49 2.9 2.9.1 Application Notes Notes on Data Access 1. Access to Empty Areas: The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur. Data transfer from CPU to empty area: The transferred data will be lost. This action may also cause the CPU to misoperate. Data transfer from empty area to CPU: Unpredictable data is transferred. 2. Access to Internal I/O Registers: Internal data transfer to or from on-chip modules other than the ROM and RAM areas makes use of an 8-bit data width. If word access is attempted to these areas, the following results will occur. Word access from CPU to I/O register area: Upper byte: Will be written to I/O register. Lower byte: Transferred data will be lost. Word access from I/O register to CPU: Upper byte: Will be written to upper part of CPU register. Lower byte: Unpredictable data will be written to lower part of CPU register. Byte size instructions should therefore be used when transferring data to or from I/O registers other than the on-chip ROM and RAM areas. Figure 2-17 shows the data size and number of states in which on-chip peripheral modules can be accessed. 50 Access States Word H'0000 H'0029 H'002A 40 kbytes* On-chip ROM 2 Interrupt vector area (42 bytes) Byte H'9FFF* Not used -- -- -- H'F780 On-chip RAM H'FF7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Notes: The H8/3935 and H8/3935R are shown as an example. * The address is H'BFFF in the H8/3936 and H8/3936R (48-kbyte on-chip ROM) and H'EDFF in the H8/3937 and H8/3937R (60-kbyte on-chip ROM). H'FF98 to H'FF9F H'FFA8 to H'FFAF -- x x x x x -- -- 2 3 2 3 2 2048 bytes 2 Figure 2-17 Data Size and Number of States for Access to and from On-Chip Peripheral Modules 51 2.9.2 Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include writeonly bits, and when the instruction accesses an I/O port. Order of Operation 1 2 3 Read Modify Write Operation Read byte data at the designated address Modify a designated bit in the read data Write the altered byte data to the designated address 1. Bit manipulation in two registers assigned to the same address Example 1: timer load register and timer counter Figure 2-18 shows an example in which two timer registers share the same address. When a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations take place. Order of Operation 1 2 3 Read Modify Write Operation Timer counter data is read (one byte) The CPU modifies (sets or resets) the bit designated in the instruction The altered byte data is written to the timer load register The timer counter is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer load register may be modified to the timer counter value. Read Count clock Timer counter Reload Write Timer load register Internal bus Figure 2-18 Timer Configuration Example 52 Example 2: BSET instruction executed designating port 3 P3 7 and P36 are designated as input pins, with a low-level signal input at P37 and a high-level signal at P3 6. The remaining pins, P35 to P30, are output pins and output low-level signals. In this example, the BSET instruction is used to change pin P30 to high-level output. [A: Prior to executing BSET] P37 Input/output Pin state PCR3 PDR3 Input Low level 0 1 P36 Input High level 0 0 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 P30 Output Low level 1 0 [B: BSET instruction executed] BSET #0 , @PDR3 The BSET instruction is executed designating port 3. [C: After executing BSET] P37 Input/output Pin state PCR3 PDR3 Input Low level 0 0 P36 Input High level 0 1 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 P30 Output High level 1 1 [D: Explanation of how BSET operates] When the BSET instruction is executed, first the CPU reads port 3. Since P37 and P36 are input pins, the CPU reads the pin states (low-level and high-level input). P3 5 to P30 are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value of H'80, but the value read by the CPU is H'40. Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU writes this value (H'41) to PDR3, completing execution of BSET. As a result of this operation, bit 0 in PDR3 becomes 1, and P3 0 outputs a high-level signal. However, bits 7 and 6 of PDR3 end up with different values. 53 To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR3. [A: Prior to executing BSET] MOV. B #80 MOV. B R0L MOV. B R0L , , , P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 1 R0L @RAM0 @PDR3 P36 Input High level 0 0 0 The PDR3 value (H'80) is written to a work area in memory (RAM0) as well as to PDR3. P35 Output Low level 1 0 0 P34 Output Low level 1 0 0 P33 Output Low level 1 0 0 P32 Output Low level 1 0 0 P31 Output Low level 1 0 0 P30 Output Low level 1 0 0 [B: BSET instruction executed] BSET #0 , @RAM0 The BSET instruction is executed designating the PDR3 work area (RAM0). [C: After executing BSET] MOV. B @RAM0, MOV. B R0L, P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 1 R0L @PDR3 P36 Input High level 0 0 0 The work area (RAM0) value is written to PDR3. P35 Output Low level 1 0 0 P34 Output Low level 1 0 0 P33 Output Low level 1 0 0 P32 Output Low level 1 0 0 P31 Output Low level 1 0 0 P30 Output High level 1 1 1 54 2. Bit manipulation in a register containing a write-only bit Example 3: BCLR instruction executed designating port 3 control register PCR3 As in the examples above, P37 and P36 are input pins, with a low-level signal input at P37 and a high-level signal at P36. The remaining pins, P35 to P30, are output pins that output low-level signals. In this example, the BCLR instruction is used to change pin P30 to an input port. It is assumed that a high-level signal will be input to this input pin. [A: Prior to executing BCLR] P37 Input/output Pin state PCR3 PDR3 Input Low level 0 1 P36 Input High level 0 0 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 P30 Output Low level 1 0 [B: BCLR instruction executed] BSET #0 , @PCR3 The BCLR instruction is executed designating PCR3. [C: After executing BCLR] P37 Input/output Pin state PCR3 PDR3 Output Low level 1 1 P36 Output High level 1 0 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 P30 Input High level 0 0 [D: Explanation of how BCLR operates] When the BCLR instruction is executed, first the CPU reads PCR3. Since PCR3 is a write-only register, the CPU reads a value of H'FF, even though the PCR3 value is actually H'3F. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. Finally, this value (H'FE) is written to PCR3 and BCLR instruction execution ends. As a result of this operation, bit 0 in PCR3 becomes 0, making P3 0 an input port. However, bits 7 and 6 in PCR3 change to 1, so that P3 7 and P36 change from input pins to output pins. 55 To avoid this problem, store a copy of the PCR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PCR3. [A: Prior to executing BCLR] MOV. B #3F MOV. B R0L MOV. B R0L , , , P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 0 R0L @RAM0 @PCR3 P36 Input High level 0 0 0 The PCR3 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR3. P35 Output Low level 1 0 1 P34 Output Low level 1 0 1 P33 Output Low level 1 0 1 P32 Output Low level 1 0 1 P31 Output Low level 1 0 1 P30 Output Low level 1 0 1 [B: BCLR instruction executed] BSET #0 , @RAM0 The BCLR instruction is executed designating the PCR3 work area (RAM0). [C: After executing BCLR] MOV. B @RAM0, MOV. B R0L, P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 0 R0L @PCR3 P36 Input High level 0 0 0 The work area (RAM0) value is written to PCR3. P35 Output Low level 1 0 1 P34 Output Low level 1 0 1 P33 Output Low level 1 0 1 P32 Output Low level 1 0 1 P31 Output Low level 1 0 1 P30 Output High level 0 0 0 56 Table 2-12 lists the pairs of registers that share identical addresses. Table 2-13 lists the registers that contain write-only bits. Table 2-12 Registers with Shared Addresses Register Name Timer counter and timer load register C Port data register 1* 1 1, 1 1 1 1 1 1 1 1 2 Abbreviation TCC/TLC PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA Address H'FFB5 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDC H'FFDD Port data register 2* * Port data register 3* Port data register 4* Port data register 5* Port data register 6* Port data register 7* Port data register 8* Port data register 9* Port data register A* Notes: 1. Port data registers have the same addresses as input pins. 2. I/O port for interfacing to FLEXTM decoder. Table 2-13 Registers with Write-Only Bits Register Name Port control register 1 Port control register 2* Port control register 3 Port control register 4 Port control register 5 Port control register 6 Port control register 7 Port control register 8 Port control register 9 Port control register A Timer control register F Note: * Abbreviation PCR1 PCR2 PCR3 PCR4 PCR5 PCR6 PCR7 PCR8 PCR9 PCRA TCRF Address H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEB H'FFEC H'FFED H'FFB6 I/O port for interfacing to FLEXTM decoder. 57 2.9.3 Notes on Use of the EEPMOV Instruction * The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 R6 R5 + R4L R6 + R4L * When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of the instruction. R5 R6 R5 + R4L H'FFFF Not allowed R6 + R4L 58 Section 3 Exception Handling 3.1 Overview Exception handling is performed in the H8/3937 Series and H8/3937R Series when a reset or interrupt occurs. Table 3-1 shows the priorities of these two types of exception handling. Table 3-1 Priority High Exception Handling Types and Priorities Exception Source Reset Interrupt Time of Start of Exception Handling Exception handling starts as soon as the reset state is cleared When an interrupt is requested, exception handling starts after execution of the present instruction or the exception handling in progress is completed Low 3.2 3.2.1 Reset Overview A reset is the highest-priority exception. The internal state of the CPU and the registers of the onchip peripheral modules are initialized. 3.2.2 Reset Sequence As soon as the RES pin goes low, all processing is stopped and the chip enters the reset state. To make sure the chip is reset properly, observe the following precautions. * At power on: Hold the RES pin low until the clock pulse generator output stabilizes. * Resetting during operation: Hold the RES pin low for at least 10 system clock cycles. Reset exception handling takes place as follows. * The CPU internal state and the registers of on-chip peripheral modules are initialized, with the I bit of the condition code register (CCR) set to 1. * The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after which the program starts executing from the address indicated in PC. 59 When system power is turned on or off, the RES pin should be held low. Figure 3-1 shows the reset sequence starting from RES input. Reset cleared Program initial instruction prefetch Vector fetch Internal processing RES o Internal address bus Internal read signal Internal write signal Internal data bus (16-bit) (1) (2) (2) (3) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) First instruction of program Figure 3-1 Reset Sequence 3.2.3 Interrupt Immediately after Reset After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized, PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To prevent this, immediately after reset exception handling all interrupts are masked. For this reason, the initial program instruction is always executed immediately after a reset. This instruction should initialize the stack pointer (e.g. MOV.W #xx: 16, SP). 60 3.3 3.3.1 Interrupts Overview The interrupt sources that initiate interrupt exception handling comprise 12 external interrupts (WKP 7 to WKP0, IRQ4 to IRQ1), 23 internal interrupts from on-chip peripheral modules, and one internal IRQ0 interrupt. Table 3-2 shows the interrupt sources, their priorities, and their vector addresses. When more than one interrupt is requested, the interrupt with the highest priority is processed. The interrupts have the following features: * Internal and external interrupts can be masked by the I bit in CCR. When the I bit is set to 1, interrupt request flags can be set but the interrupts are not accepted. * IRQ4 to IRQ0 and WKP 7 to WKP0 can be set to either rising edge sensing or falling edge sensing. 61 Table 3-2 Interrupt Sources and Their Priorities Interrupt Vector Number Vector Address Priority Reset 0 H'0000 to H'0001 High IRQ0 4 H'0008 to H'0009 IRQ1 5 H'000A to H'000B IRQ2 6 H'000C to H'000D IRQ3 7 H'000E to H'000F IRQ4 8 H'0010 to H'0011 WKP 0 9 H'0012 to H'0013 WKP 1 WKP 2 WKP 3 WKP 4 WKP 5 WKP 6 WKP 7 SCI1 transfer complete 10 H'0014 to H'0015 Timer A overflow 11 H'0016 to H'0017 Timer C overflow or 13 H'001A to H'001B underflow Timer FL Timer FL compare match 14 H'001C to H'001D Timer FL overflow Timer FH Timer FH compare match 15 H'001E to H'001F Timer FH overflow Timer G Timer G input capture 16 H'0020 to H'0021 Timer G overflow 17 H'0022 to H'0023 SCI31 SCI31 transmit end SCI31 transmit data empty SCI31 receive data full SCI31 overrrun error SCI31 framing error SCI31 parity error 18 H'0024 to H'0025 SCI32 SCI32 transmit end SCI32 transmit data empty SCI32 receive data full SCI32 overrun error SCI32 framing error SCI32 parity error A/D A/D conversion end 19 H'0026 to H'0027 (SLEEP instruction Direct transfer 20 H'0028 to H'0029 Low executed) Note: Vector addresses H'0002 to H'0007 and H'0018 to H'0019 are reserved and cannot be used. Interrupt Source RES IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 WKP 0 WKP 1 WKP 2 WKP 3 WKP 4 WKP 5 WKP 6 WKP 7 SCI1 Timer A Timer C 62 3.3.2 Interrupt Control Registers Table 3-3 lists the registers that control interrupts. Table 3-3 Name IRQ edge select register Interrupt enable register 1 Interrupt enable register 2 Interrupt request register 1 Interrupt request register 2 Wakeup interrupt request register Wakeup edge select register Note: * Interrupt Control Registers Abbreviation IEGR IENR1 IENR2 IRR1 IRR2 IWPR WEGR R/W R/W R/W R/W R/W* R/W* R/W* R/W Initial Value H'E0 H'00 H'00 H'20 H'00 H'00 H'00 Address H'FFF2 H'FFF3 H'FFF4 H'FFF6 H'FFF7 H'FFF9 H'FF90 Write is enabled only for writing of 0 to clear a flag. 1. IRQ edge select register (IEGR) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 IEG4 0 R/W 3 IEG3 0 R/W 2 IEG2 0 R/W 1 IEG1 0 R/W 0 IEG0 0 R/W IEGR is an 8-bit read/write register used to designate whether pins IRQ4 to IRQ 1, and the internal IRQ 0 signal used to interface to the FLEXTM decoder, are set to rising edge sensing or falling edge sensing. Bits 7 to 5: Reserved bits Bits 7 to 5 are reserved: they are always read as 1 and cannot be modified. Bit 4: IRQ4 edge select (IEG4) Bit 4 selects the input sensing of the IRQ4 pin and ADTRG pin. Bit 4 IEG4 0 1 Description Falling edge of IRQ4 and ADTRG pin input is detected Rising edge of IRQ4 and ADTRG pin input is detected (initial value) 63 Bit 3: IRQ3 edge select (IEG3) Bit 3 selects the input sensing of the IRQ3 pin and TMIF pin. Bit 3 IEG3 0 1 Description Falling edge of IRQ3 and TMIF pin input is detected Rising edge of IRQ3 and TMIF pin input is detected (initial value) Bit 2: IRQ2 edge select (IEG2) Bit 2 selects the input sensing of pin IRQ2. Bit 2 IEG2 0 1 Description Falling edge of IRQ2 pin input is detected Rising edge of IRQ2 pin input is detected (initial value) Bit 1: IRQ1 edge select (IEG1) Bit 3 selects the input sensing of the IRQ1 pin and TMIC pin. Bit 1 IEG1 0 1 Description Falling edge of IRQ1 and TMIC pin input is detected Rising edge of IRQ1 and TMIC pin input is detected (initial value) Bit 0: IRQ0 edge select (IEG0) Bit 0 selects the input sensing of the IRQ0 signal. Bit 0 IEG0 0 1 Description Falling edge of IRQ0 signal input is detected Rising edge of IRQ0 signal input is detected (initial value) Note: IRQ0 is an internal signal that performs interfacing to the FLEXTM decoder incorporated in the chip. 64 2. Interrupt enable register 1 (IENR1) Bit Initial value Read/Write 7 IENTA 0 R/W 6 IENS1 0 R/W 5 IENWP 0 R/W 4 IEN4 0 R/W 3 IEN3 0 R/W 2 IEN2 0 R/W 1 IEN1 0 R/W 0 IEN0 0 R/W IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7: Timer A interrupt enable (IENTA) Bit 7 enables or disables timer A overflow interrupt requests. Bit 7 IENTA 0 1 Description Disables timer A interrupt requests Enables timer A interrupt requests (initial value) Bit 6: SCI1 interrupt enable (IENS1) Bit 6 enables or disables SCI1 transfer complete interrupt requests. Bit 6 IENS1 0 1 Description Disables SCI1 interrupt requests Enables SCI1 interrupt requests (initial value) Note: SCI1 is an internal function that performs interfacing to the FLEXTM decoder incorporated in the chip. Bit 5: Wakeup interrupt enable (IENWP) Bit 5 enables or disables WKP7 to WKP0 interrupt requests. Bit 5 IENWP 0 1 Description Disables WKP 7 to WKP 0 interrupt requests Enables WKP 7 to WKP 0 interrupt requests (initial value) 65 Bits 4 to 0: IRQ4 to IRQ0 interrupt enable (IEN4 to IEN0) Bits 4 to 0 enable or disable IRQ4 to IRQ0 interrupt requests. Bit n IENn 0 1 Description Disables interrupt requests from pin IRQn Enables interrupt requests from pin IRQn (n = 4 to 0) Note: IRQ0 is an internal signal that performs interfacing to the FLEXTM decoder incorporated in the chip. (initial value) 3. Interrupt enable register 2 (IENR2) Bit Initial value Read/Write 7 IENDT 0 R/W 6 IENAD 0 R/W 5 -- 0 R/W 4 IENTG 0 R/W 3 0 R/W 2 0 R/W 1 IENTC 0 R/W 0 IENEC 0 R/W IENTFH IENTFL IENR2 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7: Direct transfer interrupt enable (IENDT) Bit 7 enables or disables direct transfer interrupt requests. Bit 7 IENDT 0 1 Description Disables direct transfer interrupt requests Enables direct transfer interrupt requests (initial value) Bit 6: A/D converter interrupt enable (IENAD) Bit 6 enables or disables A/D converter interrupt requests. Bit 6 IENAD 0 1 Description Disables A/D converter interrupt requests Enables A/D converter interrupt requests (initial value) Bit 5: Reserved bit Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset. 66 Bit 4: Timer G interrupt enable (IENTG) Bit 4 enables or disables timer G input capture or overflow interrupt requests. Bit 4 IENTG 0 1 Description Disables timer G interrupt requests Enables timer G interrupt requests (initial value) Bit 3: Timer FH interrupt enable (IENTFH) Bit 3 enables or disables timer FH compare match and overflow interrupt requests. Bit 3 IENTFH 0 1 Description Disables timer FH interrupt requests Enables timer FH interrupt requests (initial value) Bit 2: Timer FL interrupt enable (IENTFL) Bit 2 enables or disables timer FL compare match and overflow interrupt requests. Bit 2 IENTFL 0 1 Description Disables timer FL interrupt requests Enables timer FL interrupt requests (initial value) Bit 1: Timer C interrupt enable (IENTC) Bit 1 enables or disables timer C overflow and underflow interrupt requests. Bit 1 IENTC 0 1 Description Disables timer C interrupt requests Enables timer C interrupt requests (initial value) Bit 0: Reserved bit Bit 0 is reserved: it is always read as 0 and cannot be modified. For details of SCI31 interrupt control, see 6. Serial control register 3 (SCR3) in section 10.3.2. 67 4. Interrupt request register 1 (IRR1) Bit Initial value Read/Write 7 IRRTA 0 R/(W)* 6 IRRS1 0 R/(W)* 5 -- 1 -- 4 IRRI4 0 R/(W)* 3 IRRI3 0 R/(W)* 2 IRRI2 0 R/(W)* 1 IRRI1 0 R/(W)* 0 IRRI0 0 R/(W)* Note: * Only a write of 0 for flag clearing is possible IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A, SCI1, or IRQ 4 to IRQ0 interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. Bit 7: Timer A interrupt request flag (IRRTA) Bit 7 IRRTA 0 1 Description Clearing conditions: When IRRTA = 1, it is cleared by writing 0 Setting conditions: When the timer A counter value overflows from H'FF to H'00 (initial value) Bit 6: SCI1 interrupt request flag (IRRS1) Bit 6 IRRS1 0 1 Description Clearing conditions: When IRRS1 = 1, it is cleared by writing 0 Setting conditions: When SCI1 completes transfer (initial value) Note: SCI1 is an internal function that performs interfacing to the FLEXTM decoder incorporated in the chip. Bit 5: Reserved bit Bit 5 is reserved; it is always read as 1 and cannot be modified. 68 Bits 4 to 0: IRQ4 to IRQ0 interrupt request flags (IRRI4 to IRRI0) Bit n IRRIn 0 1 Description Clearing conditions: When IRRIn = 1, it is cleared by writing 0 Setting conditions: When pin IRQn is designated for interrupt input and the designated signal edge is input (n = 4 to 0) Note: IRQ0 is an internal signal that performs interfacing to the FLEXTM decoder incorporated in the chip. (initial value) 5. Interrupt request register 2 (IRR2) Bit Initial value Read/Write 7 IRRDT 0 R/(W)* 6 IRRAD 0 R/(W)* 5 -- 0 R/W 4 IRRTG 0 R/(W)* 3 0 R/(W)* 2 0 R/(W)* 1 IRRTC 0 R/(W)* 0 IRREC 0 R/(W)* IRRTFH IRRTFL Note: * Only a write of 0 for flag clearing is possible IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct transfer, A/D converter, Timer G, Timer FH, Timer FC, or Timer C interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. Bit 7: Direct transfer interrupt request flag (IRRDT) Bit 7 IRRDT 0 1 Description Clearing conditions: When IRRDT = 1, it is cleared by writing 0 Setting conditions: When a direct transfer is made by executing a SLEEP instruction while DTON = 1 in SYSCR2 (initial value) 69 Bit 6: A/D converter interrupt request flag (IRRAD) Bit 6 IRRAD 0 1 Description Clearing conditions: When IRRAD = 1, it is cleared by writing 0 Setting conditions: When A/D conversion is completed and ADSF is cleared to 0 in ADSR (initial value) Bit 5: Reserved bit Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset. Bit 4: Timer G interrupt request flag (IRRTG) Bit 4 IRRTG 0 1 Description Clearing conditions: When IRRTG = 1, it is cleared by writing 0 (initial value) Setting conditions: When the TMIG pin is designated for TMIG input and the designated signal edge is input, and when TCG overflows while OVIE is set to 1 in TMG Bit 3: Timer FH interrupt request flag (IRRTFH) Bit 3 IRRTFH 0 1 Description Clearing conditions: When IRRTFH = 1, it is cleared by writing 0 (initial value) Setting conditions: When TCFH and OCRFH match in 8-bit timer mode, or when TCF (TCFL, TCFH) and OCRF (OCRFL, OCRFH) match in 16-bit timer mode Bit 2: Timer FL interrupt request flag (IRRTFL) Bit 2 IRRTFL 0 1 Description Clearing conditions: When IRRTFL= 1, it is cleared by writing 0 Setting conditions: When TCFL and OCRFL match in 8-bit timer mode (initial value) 70 Bit 1: Timer C interrupt request flag (IRRTC) Bit 1 IRRTC 0 1 Description Clearing conditions: When IRRTC= 1, it is cleared by writing 0 (initial value) Setting conditions: When the timer C counter value overflows (from H'FF to H'00) or underflows (from H'00 to H'FF) Bit 0: Reserved bit Bit 0 is reserved: it is always read as 0 and cannot be modified. 6. Wakeup Interrupt Request Register (IWPR) Bit Initial value Read/Write Note: * 7 IWPF7 0 R/(W)* 6 IWPF6 0 R/(W)* 5 IWPF5 0 R/(W)* 4 IWPF4 0 R/(W)* 3 IWPF3 0 R/(W)* 2 IWPF2 0 R/(W)* 1 IWPF1 0 R/(W)* 0 IWPF0 0 R/(W)* All bits can only be written with 0, for flag clearing. IWPR is an 8-bit read/write register containing wakeup interrupt request flags. When one of pins WKP7 to WKP0 is designated for wakeup input and a rising or falling edge is input at that pin, the corresponding flag in IWPR is set to 1. A flag is not cleared automatically when the corresponding interrupt is accepted. Flags must be cleared by writing 0. Bits 7 to 0: Wakeup interrupt request flags (IWPF7 to IWPF0) Bit n IWPFn 0 1 Description Clearing conditions: When IWPFn= 1, it is cleared by writing 0 (initial value) Setting conditions: When pin WKP n is designated for wakeup input and a rising or falling edge is input at that pin (n = 7 to 0) 71 7. Wakeup Edge Select Register (WEGR) Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins WKPn. WEGR is initialized to H'00 by a reset. Bit n: WKPn edge select (WKEGSn) Bit n selects WKPn pin input sensing. Bit n WKEGS 0 1 Description WKPn pin falling edge detected WKPn pin rising edge detected (n = 7 to 0) (initial value) 3.3.3 External Interrupts There are 12 external interrupts: IRQ 4 to IRQ0 and WKP 7 to WKP0. 1. Interrupts WKP 7 to WKP0 Interrupts WKP 7 to WKP0 are requested by either rising or falling edge input to pins WKP7 to WKP0. When these pins are designated as pins WKP7 to WKP0 in port mode register 5 and a rising or falling edge is input, the corresponding bit in IWPR is set to 1, requesting an interrupt. Recognition of wakeup interrupt requests can be disabled by clearing the IENWP bit to 0 in IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR. When WKP 7 to WKP0 interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector number 9 is assigned to interrupts WKP7 to WKP0. All eight interrupt sources have the same vector number, so the interrupt-handling routine must discriminate the interrupt source. 2. Interrupts IRQ 4 to IRQ1 Interrupts IRQ4 to IRQ 1 are requested by input signals to pins IRQ4 to IRQ1. These interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG 4 to IEG1 in IEGR. 72 When these pins are designated as pins IRQ4 to IRQ1 in port mode register 3 and 1 and the designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt. Recognition of these interrupt requests can be disabled individually by clearing bits IEN4 to IEN1 to 0 in IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR. When IRQ 4 to IRQ1 interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector numbers 8 to 5 are assigned to interrupts IRQ4 to IRQ1. The order of priority is from IRQ1 (high) to IRQ4 (low). Table 3-2 gives details. 3.3.4 Internal Interrupts 1. Internal interrupts There are 23 internal interrupts that can be requested by the on-chip peripheral modules. When a peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1. Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in IENR1 or IENR2. All these interrupts can be masked by setting the I bit to 1 in CCR. When internal interrupt handling is initiated, the I bit is set to 1 in CCR. Vector numbers from 20 to 13, 11, and 10 are assigned to these interrupts. Table 3-2 shows the order of priority of interrupts from on-chip peripheral modules. 2. IRQ0 interrupt The IRQ0 interrupt is requested by the READY input signal from the FLEXTM decoder incorporated in the chip. Rising or falling edge sensing can be selected for the IRQ0 interrupt by means of bit IEG0 in IEGR. When the designated edge is input while the IRQ0 function is selected by bit IRQ0 in PMR3, bit IRRI0 is set to 1 in IRR1, and an interrupt is requested. Interrupt request recognition can be disabled by clearing bit IEN0 to 0 in IENR1. In addition, all interrupts can be masked by setting the I bit to 1 in CCR. When IRQ 0 interrupt exception handling is initiated, the I bit is set to 1 in CCR. The vector number for IRQ0 interrupt exception handling is 4. See table 3-2 for details. 73 3.3.5 Interrupt Operations Interrupts are controlled by an interrupt controller. Figure 3-2 shows a block diagram of the interrupt controller. Figure 3-3 shows the flow up to interrupt acceptance. Interrupt controller External or internal interrupts Priority decision logic Interrupt request External interrupts or internal interrupt enable signals I CCR (CPU) Figure 3-2 Block Diagram of Interrupt Controller Interrupt operation is described as follows. * When an interrupt condition is met while the interrupt enable register bit is set to 1, an interrupt request signal is sent to the interrupt controller. * When the interrupt controller receives an interrupt request, it sets the interrupt request flag. * From among the interrupts with interrupt request flags set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending. (Refer to table 3-2 for a list of interrupt priorities.) * The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request is accepted; if the I bit is 1, the interrupt request is held pending. 74 * If the interrupt is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3-4. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. * The I bit of CCR is set to 1, masking further interrupts. * The vector address corresponding to the accepted interrupt is generated, and the interrupt handling routine located at the address indicated by the contents of the vector address is executed. Notes: 1. When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt request register, always do so while interrupts are masked (I = 1). 2. If the above clear operations are performed while I = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception processing for the interrupt will be executed after the clear instruction has been executed. 75 Program execution state IRRI0 = 1 Yes IEN0 = 1 Yes No No No IRRI1 = 1 Yes IEN1 = 1 Yes No No IRRI2 = 1 Yes IEN2 = 1 Yes No IRRDT = 1 Yes IENDT = 1 Yes No No No I=0 Yes PC contents saved CCR contents saved I1 Branch to interrupt handling routine Notation: PC: Program counter CCR: Condition code register I: I bit of CCR Figure 3-3 Flow up to Interrupt Acceptance 76 SP - 4 SP - 3 SP - 2 SP - 1 SP (R7) Stack area SP (R7) SP + 1 SP + 2 SP + 3 SP + 4 CCR CCR * PCH PCL Even address Prior to start of interrupt exception handling Notation: PCH: Upper 8 bits of program counter (PC) Lower 8 bits of program counter (PC) PCL: CCR: Condition code register Stack pointer SP: PC and CCR saved to stack After completion of interrupt exception handling Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt handling routine. 2. Register contents must always be saved and restored by word access, starting from an even-numbered address. * Ignored on return. Figure 3-4 Stack State after Completion of Interrupt Exception Handling Figure 3-5 shows a typical interrupt sequence. 77 78 Interrupt is accepted Instruction prefetch Internal processing Stack access Vector fetch Prefetch instruction of Internal interrupt-handling routine processing (1) (3) (5) (6) (8) (9) (2) (4) (1) (7) (9) (10) Interrupt level decision and wait for end of instruction Interrupt request signal o Internal address bus Internal read signal Figure 3-5 Interrupt Sequence Internal write signal Internal data bus (16 bits) (1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.) (5) SP - 2 (6) SP - 4 (7) CCR (8) Vector address (9) Starting address of interrupt-handling routine (contents of vector) (10) First instruction of interrupt-handling routine 3.3.6 Interrupt Response Time Table 3-4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3-4 Item Waiting time for completion of executing instruction* Saving of PC and CCR to stack Vector fetch Instruction fetch Internal processing Note: * Not including EEPMOV instruction. Interrupt Wait States States 1 to 13 4 2 4 4 Total 15 to 27 79 3.4 3.4.1 Application Notes Notes on Stack Area Use When word data is accessed in the H8/3937 Series and H8/3937R Series, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @-SP) or POP Rn (MOV.W @SP+, Rn) to save or restore register values. Setting an odd address in SP may cause a program to crash. An example is shown in figure 3-6. SP SP PCH PC L SP R1L PC L H'FEFC H'FEFD H'FEFF BSR instruction SP set to H'FEFF MOV. B R1L, @-R7 Contents of PCH are lost Stack accessed beyond SP Notation: PCH: Upper byte of program counter PCL: Lower byte of program counter R1L: General register R1L SP: Stack pointer Figure 3-6 Operation when Odd Address is Set in SP When CCR contents are saved to the stack during interrupt exception handling or restored when RTE is executed, this also takes place in word size. Both the upper and lower bytes of word data are saved to the stack; on return, the even address contents are restored to CCR while the odd address contents are ignored. 80 3.4.2 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. When an external interrupt pin function is switched by rewriting the port mode register that controls pins IRQ4 to IRQ1, WKP7 to WKP0, the interrupt request flag may be set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin. Be sure to clear the interrupt request flag to 0 after switching pin functions. Similarly, when the pin function is switched by rewriting the port mode register that controls IRQ 0, the interrupt request flag may be set to 1 at the time the pin function is switched, even if no valid interrupt is input. Therefore, be sure to clear the interrupt request flag to 0 after switching the pin function. Table 3-5 shows the conditions under which interrupt request flags are set to 1 in this way. 81 Table 3-5 Conditions under which Interrupt Request Flag is Set to 1 Conditions When PMR1 bit IRQ4 is changed from 0 to 1 while pin IRQ4 is low and IEGR bit IEG4 = 0. When PMR1 bit IRQ4 is changed from 1 to 0 while pin IRQ4 is low and IEGR bit IEG4 = 1. When PMR1 bit IRQ3 is changed from 0 to 1 while pin IRQ3 is low and IEGR bit IEG3 = 0. When PMR1 bit IRQ3 is changed from 1 to 0 while pin IRQ3 is low and IEGR bit IEG3 = 1. When PMR1 bit IRQ2 is changed from 0 to 1 while pin IRQ2 is low and IEGR bit IEG2 = 0. When PMR1 bit IRQ2 is changed from 1 to 0 while pin IRQ2 is low and IEGR bit IEG2 = 1. When PMR1 bit IRQ1 is changed from 0 to 1 while pin IRQ1 is low and IEGR bit IEG1 = 0. When PMR1 bit IRQ1 is changed from 1 to 0 while pin IRQ1 is low and IEGR bit IEG1 = 1. When PMR3 bit IRQ0 is changed from 0 to 1 while IRQ0 is low and IEGR bit IEG0 = 0. When PMR3 bit IRQ0 is changed from 1 to 0 while IRQ0 is low and IEGR bit IEG0 = 1. When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP 7 is low. When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP 6 is low. When PMR5 bit WKP5 is changed from 0 to 1 while pin WKP 5 is low. When PMR5 bit WKP4 is changed from 0 to 1 while pin WKP 4 is low. When PMR5 bit WKP3 is changed from 0 to 1 while pin WKP 3 is low. When PMR5 bit WKP2 is changed from 0 to 1 while pin WKP 2 is low. When PMR5 bit WKP1 is changed from 0 to 1 while pin WKP 1 is low. When PMR5 bit WKP0 is changed from 0 to 1 while pin WKP 0 is low. Interrupt Request Flags Set to 1 IRR1 IRRI4 IRRI3 IRRI2 IRRI1 IRRI0 IWPR IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Figure 3-7 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0. If the instruction to clear the flag is executed immediately after the port mode register access without executing an intervening instruction, the flag will not be cleared. An alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3-5 do not occur. 82 CCR I bit 1 Interrupts masked. (Another possibility is to disable the relevant interrupt in interrupt enable register 1.) Set port mode register bit Execute NOP instruction Clear interrupt request flag to 0 After setting the port mode register bit, first execute at least one instruction (e.g., NOP), then clear the interrupt request flag to 0 CCR I bit 0 Interrupt mask cleared Figure 3-7 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure 3.4.3 Notes on Interrupt Request Flag Clearing Methods Either of the following methods should be used for flag clearing in the interrupt request registers (IRR1, IRR2, IWPR). Method 1 Clear the interrupt request flag with a BCLR instruction. (Recommended method) Sample coding for clearing IRRI1 (bit 1 of IRR1): BCLR #1,@IRR1:8 Method 2 Write data to the interrupt request register with 0 for the relevant interrupt request flag and 1s for the other flags. (Faster execution than Method 1) Sample coding for clearing IRRI1 (bit 1 of IRR1): MOV.B #B'11111101,R1L MOV.B R1L,@IRR1:8 83 84 Section 4 Clock Pulse Generators 4.1 Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. 4.1.1 Block Diagram Figure 4-1 shows a block diagram of the clock pulse generators. OSC 1 OSC 2 System clock oscillator oOSC (f OSC) oOSC/2 System clock divider (1/2) System clock divider oOSC/128 oOSC/64 oOSC/32 oOSC/16 o Prescaler S (13 bits) o/2 to o/8192 oDEC oW oSUB oW /2 oW /4 oW /8 to oW /128 System clock pulse generator oW /2 oW /4 oW /8 DX1 DX2 Subclock oscillator Subclock oscillator (1/2) oW (f W ) Subclock divider (1/2, 1/4, 1/8) Subclock pulse generator Prescaler W (5 bits) Figure 4-1 Block Diagram of Clock Pulse Generators 4.1.2 System Clock and Subclock The basic clock signals that drive the CPU and on-chip peripheral modules are o and oSUB. Five of the clock signals have names: o is the system clock, o SUB is the subclock, oOSC is the oscillator clock, o w is the watch clock, and oDEC is the decoder clock. The clock signals available for use by peripheral modules are o/2, o/4, o/8, o/16, o/32, o/64, o/128, o/256, o/512, o/1024, o/2048, o/4096, o/8192, o W , oW /2, oW /4, oW /8, oW /16, oW /32, oW /64, oW /128, and oDEC. The clock requirements differ from one module to another. 85 4.2 System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. 1. Connecting a crystal oscillator Figure 4-2 shows a typical method of connecting a crystal oscillator. C1 OSC 1 Rf OSC 2 C2 R f = 1 M 20% Oscillation frequency Manufacturer 4.0 MHz Recommended value for C1 and C2 Nihon Denpa Kogyo 12 pF 20% Figure 4-2 Typical Connection to Crystal Oscillator Figure 4-3 shows the equivalent circuit of a crystal oscillator. An oscillator having the characteristics given in table 4-1 should be used. CS LS OSC 1 RS OSC 2 C0 Figure 4-3 Equivalent Circuit of Crystal Oscillator Table 4-1 Frequency RS (max) C0 (max) Crystal Oscillator Parameters 4.193 MHz 100 16 pF 86 2. Connecting a ceramic oscillator Figure 4-4 shows a typical method of connecting a ceramic oscillator. C1 OSC 1 Rf OSC 2 C2 R f = 1 M 20% Oscillation frequency Manufacturer 4.0 MHz Murata Seisakusho Recommended value for C1 and C2 30 pF 10% Figure 4-4 Typical Connection to Ceramic Oscillator 3. Notes on board design When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points. Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (See figure 4-5.) The board should be designed so that the oscillator and load capacitors are located as close as possible to pins OSC1 and OSC2. To be avoided Signal A Signal B C1 OSC 1 OSC 2 C2 Figure 4-5 Board Design of Oscillator Circuit 87 4. External clock input method Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 4-6 shows a typical connection. OSC 1 OSC 2 External clock input Open Figure 4-6 External Clock Input (Example) Frequency Duty cycle Oscillator Clock (oOSC) 45% to 55% Caution When a crystal or ceramic oscillator element is connected, circuit constants will differ according to the oscillator element, installation circuit stray capacitance, and so forth, and so should be determined in consultation with the crystal or ceramic oscillator element manufacturer. 88 4.3 Subclock Generator 1. Connecting a 76.8-kHz/160-kHz crystal oscillator Clock pulses can be supplied to the subclock divider by connecting a 76.8-kHz/160-kHz crystal oscillator, as shown in figure 4-7. Follow the same precautions as noted under 3. notes on board design for the system clock in 4.2. C1 DX 1 DX 2 C2 C1 = C 2 = 12.5 pF (typ.) Figure 4-7 Typical Connection to 76.8-kHz/160-kHz Crystal Oscillator (Subclock) Figure 4-8 shows the equivalent circuit of the 76.8-kHz/160-kHz crystal oscillator. CS LS RS DX 1 DX 2 C0 fW = 76.8 kHz/160 kHz Figure 4-8 Equivalent Circuit of 76.8-kHz/160-kHz Crystal Oscillator 2. Pin connection when not using subclock When the subclock is not used, connect pin DX1 to GND and leave pin DX2 open, as shown in figure 4-9. DX 1 DX 2 GND Open Figure 4-9 Pin Connection when not Using Subclock 89 3. External clock input Connect the external clock to the DX1 pin and leave the DX2 pin open, as shown in figure 4-10. DX 1 External clock input DX 2 Open Figure 4-10 Pin Connection when Inputting External Clock Frequency Duty Subclock (ow) 45% to 55% 90 4.4 Prescalers The H8/3937 Series and 3937R Series are equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (o) as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules. Prescaler W is a 5-bit counter using a 38.4 kHz or 80 kHz signal, obtained by dividing a 76.8 kHz or 160 kHz signal by 2, further divided by 4 (ow/4) as its input clock. Its prescaled outputs are used for timer A time-base operations. 1. Prescaler S (PSS) Prescaler S is a 13-bit counter using the system clock (o) as its input clock. It is incremented once per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state. In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write prescaler S. The output from prescaler S is shared by timer A, timer C, timer F, timer G, SCI1, SCI31, SC32, the A/D converter, and the watchdog timer. The divider ratio can be set separately for each onchip peripheral function. In active (medium-speed) mode the clock input to prescaler S is oosc/16, oosc/32, oosc/64, or oosc/128. 2. Prescaler W (PSW) Prescaler W is a 5-bit counter using a 38.4 kHz or 80 kHz signal, obtained by dividing a 76.8 kHz or 160 kHz signal by 2, further divided by 4 (ow/4) as its input clock. Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state. Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues functioning so long as clock signals are supplied to pins DX1 and DX2. Prescaler W can be reset by setting 1 in bits TMA3 and TMA2 of timer mode register A (TMA). Output from prescaler W can be used to drive timer A, in which case timer A functions as a time base. 91 4.5 Note on Oscillators Oscillator characteristics are closely related to board design and should be carefully evaluated by the user in mask ROM and ZTATTM versions, referring to the examples shown in this section. Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the oscillator element manufacturer. Design the circuit so that the oscillator element never receives voltages exceeding its maximum rating. 4.5.1 Definition of Oscillation Settling Standby Time Figure 4-11 shows the oscillation waveform (OSC2), system clock (o), and microcomputer operating mode when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock oscillator. As shown in figure 4-11, as the system clock oscillator is halted in standby mode, watch mode, and subactive mode, when a transition is made to active (high-speed/medium-speed) mode, the sum of the following two times (oscillation settling time and standby time) is required. 1. Oscillation settling time (trc) The time from the point at which the system clock oscillator oscillation waveform starts to change when an interrupt is generated, until the amplitude of the oscillation waveform increases and the oscillation frequency stabilizes. 2. Standby time The time required for the CPU and peripheral functions to begin operating after the oscillation waveform frequency and system clock have stabilized. The standby time setting is selected with standby timer select bits 2 to 0 (STS2 to STS0) (bits 6 to 4 in system control register 1 (SYSCR1)). 92 Oscillation waveform (OSC2) System clock (o) Oscillation settling time Standby time Operating mode Standby mode, watch mode, or subactive mode Oscillation settling standby time Active (high-speed) mode or active (medium-speed) mode Interrupt accepted Figure 4-11 Oscillation Settling Standby Time When standby mode, watch mode, or subactive mode is cleared by an interrupt or reset, and a transition is made to active (high-speed/medium-speed) mode, the oscillation waveform begins to change at the point at which the interrupt is accepted. Therefore, when an oscillator element is connected in standby mode, watch mode, or subactive mode, since the system clock oscillator is halted, the time from the point at which this oscillation waveform starts to change until the amplitude of the oscillation waveform increases and the oscillation frequency stabilizes--that is, the oscillation settling time--is required. The oscillation settling time in the case of these state transitions is the same as the oscillation settling time at power-on (the time from the point at which the power supply voltage reaches the prescribed level until the oscillation stabilizes), specified by "oscillation settling time trc" in the AC characteristics. Meanwhile, once the system clock has halted, a standby time of at least 8 states is necessary in order for the CPU and peripheral functions to operate normally. Thus, the time required from interrupt generation until operation of the CPU and peripheral functions is the sum of the above described oscillation settling time and standby time. This total time is called the oscillation settling standby time, and is expressed by equation (1) below. Oscillation settling standby time = oscillation settling time + standby time = trc + (8 to 16,384 states) ................. (1) 93 Therefore, when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock oscillator, careful evaluation must be carried out on the installation circuit before deciding on the oscillation settling standby time. In particular, since the oscillation settling time is affected by installation circuit constants, stray capacitance, and so forth, suitable constants should be determined in consultation with the oscillator element manufacturer. 4.5.2 Notes on Use of Crystal Oscillator Element (Excluding Ceramic Oscillator Element) When a microcomputer operates, the internal power supply potential fluctuates slightly in synchronization with the system clock. Depending on the individual crystal oscillator element characteristics, the oscillation waveform amplitude may not be sufficiently large immediately after the oscillation settling standby time, making the oscillation waveform susceptible to influence by fluctuations in the power supply potential. In this state, the oscillation waveform may be disrupted, leading to an unstable system clock and erroneous operation of the microcomputer. If erroneous operation occurs, change the setting of standby timer select bits 2 to 0 (STS2 to STS0) (bits 6 to 4 in system control register 1 (SYSCR1)) to give a longer standby time. For example, if erroneous operation occurs with a standby time setting of 16 states, check the operation with a standby time setting of 1,024 states or more. If the same kind of erroneous operation occurs after a reset as after a state transition, hold the RES pin low for a longer period. 94 Section 5 Power-Down Modes 5.1 Overview The H8/3937 Series and H8/3937R Series have nine modes of operation after a reset. These include eight power-down modes, in which power dissipation is significantly reduced. Table 5-1 gives a summary of the eight operating modes. Table 5-1 Operating Modes Description The CPU and all on-chip peripheral functions are operable on the system clock in high-speed operation. The FLEXTM decoder is independently operable on the subclock. The CPU and all on-chip peripheral functions are operable on the system clock in low-speed operation. The FLEXTM decoder is independently operable on the subclock. The CPU is operable on the subclock in low-speed operation. The FLEXTM decoder is independently operable on the subclock. The CPU halts. On-chip peripheral functions are operable on the system clock. The FLEXTM decoder is independently operable on the subclock. The CPU halts. On-chip peripheral functions operate at a frequency of 1/64, 1/32, 1/16, or 1/8 of the system clock frequency. The FLEXTM decoder is independently operable on the subclock. The CPU halts. Timer A, timer C, timer G, timer F, the WDT, SCI1, SCI31, SCI32, and the FLEXTM decoder are operable on the subclock. The timer A time-base function, timer F, timer G, and the FLEXTM decoder are operable on the subclock. The CPU and all on-chip peripheral functions halt. The FLEXTM decoder is independently operable on the subclock. Individual on-chip peripheral functions specified by software enter standby mode and halt. Operating Mode Active (high-speed) mode Active (medium-speed) mode Subactive mode Sleep (high-speed) mode Sleep (medium-speed) mode Subsleep mode Watch mode Standby mode Module standby mode Of these nine operating modes, all but the active (high-speed) mode are power-down modes. In this section the two active modes (high-speed and medium speed) will be referred to collectively as active mode. Figure 5-1 shows the transitions among these operation modes. Table 5-2 indicates the internal states in each mode. 95 Reset state Program execution state Active (high-speed) mode SLEEP instruction*a *3 Program halt state Sleep (high-speed) mode Program halt state P *d EE n SL uctio r t ins *4 Standby mode SL instr EEP uctio *d n *4 ins SLEE tru ctio P n *e Active (medium-speed) mode * EP n LE ctio S ru st inin SL st E ru EP ct io n *b SLEEP instruction*b *3 a SLEEP instruction*g SLEEP instruction*f Sleep (medium-speed) mode SLEEP instruction*h *1 *1 Watch mode SLEEP instruction*e *1 SLEEP instruction*i *e EP n LE ctio S ru st in Subactive mode ins SLEE tru P cti on *j SL ins E tru EP ctio n *i SLEEP instruction*c *2 Subsleep mode Power-down modes Mode Transition Conditions (1) LSON MSON SSBY TMA3 DTON a b c d e f g h i J 0 0 1 0 0 1 0 0 0 1 1 0 0 1 1 1 Mode Transition Conditions (2) Interrupt Sources 1 2 Timer A, Timer F, Timer G interrupt, IRQ0 interrupt, WKP7 to WKP0 interrupt Timer A, Timer C, Timer F, Timer G, SCI1, SCI31, SCI32 interrupt, IRQ4 to IRQ0 interrupts, WKP7 to WKP0 interrupts All interrupts IRQ1 or IRQ0 interrupt, WKP7 to WKP0 interrupts * * 1 0 1 * 0 0 0 1 0 * * * 0 1 1 * * 1 1 1 * 0 0 0 0 0 0 1 1 1 1 1 3 4 * Don't care Notes: 1. A transition between different modes cannot be made to occur simply because an interrupt request is generated. Make sure that interrupt handling is performed after the interrupt is accepted. 2. Details on the mode transition conditions are given in the explanations of each mode, in sections 5-2 through 5-8. Figure 5-1 Mode Transition Diagram 96 Table 5-2 Internal State in Each Operating Mode Active Mode Sleep Mode HighSpeed Functions Functions Halted Retained MediumSpeed Functions Functions Halted Retained Watch Mode Halted Functions Halted Retained Subactive Subsleep Mode Mode Halted Functions Functions Halted Functions Halted Retained Standby Mode Halted Functions Halted Retained Retained* 1 Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Retained* 5 HighSpeed Functions Functions MediumSpeed Functions Functions Functions Function System clock oscillator Subclock oscillator CPU operations RAM Registers I/O ports IRQ0 interrupt External interrupts IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 WKP0 WKP1 WKP2 WKP3 WKP4 WKP5 WKP6 WKP7 Peripheral Timer A functions Timer C WDT Timer G, Timer F SCI1 SCI31, SCI32 A/D converter FLEXTM decoder Notes: 1. 2. 3. 4. 5. 6. 7. Instructions Functions Retained* 5 Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions*4 Functions*4 Functions*4 Retained Retained Functions/ Functions/ Retained Retained* 2 Retained* 2 Functions/ Retained Retained* 7 Functions/ Functions/ Functions/ Retained* 6 Retained* 2 Retained* 2 Retained Reset Retained Functions Functions/ Functions/ Retained Retained* 2 Retained* 2 Functions/ Functions/ Reset Retained* 3 Retained* 3 Retained Functions Retained Functions Retained Functions Register contents are retained, but output is high-impedance state. Functions if an external clock or the oW/4 internal clock is selected; otherwise halted and retained. Functions if oW /2 is selected as the internal clock; otherwise halted and retained. Functions if the time-base function is selected. External interrupt requests are ignored. Interrupt request register contents are not altered. Functions if oW /4 is selected as the external or internal clock; otherwise halted and retained. Functions if oW /32 is selected as the internal clock; otherwise halted and retained. 97 5.1.1 System Control Registers The operation mode is selected using the system control registers described in table 5-3. Table 5-3 Name System control register 1 System control register 2 System Control Registers Abbreviation SYSCR1 SYSCR2 R/W R/W R/W Initial Value H'07 H'F0 Address H'FFF0 H'FFF1 1. System control register 1 (SYSCR1) Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 LSON 0 R/W 2 -- 1 -- 1 MA1 1 R/W 0 MA0 1 R/W SYSCR1 is an 8-bit read/write register for control of the power-down modes. Upon reset, SYSCR1 is initialized to H'07. Bit 7: Software standby (SSBY) This bit designates transition to standby mode or watch mode. Bit 7 SSBY 0 Description * * 1 * * When a SLEEP instruction is executed in active mode, a transition (initial value) is made to sleep mode When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode When a SLEEP instruction is executed in active mode, a transition is made to standby mode or watch mode When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode 98 Bits 6 to 4: Standby timer select 2 to 0 (STS2 to STS0) These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. The designation should be made according to the operating frequency so that the waiting time is at least equal to the oscillation settling time. Bit 6 STS2 0 0 0 0 1 1 1 1 Bit 5 STS1 0 0 1 1 0 0 1 1 Bit 4 STS0 0 1 0 1 0 1 0 1 Description Wait time = 8,192 states Wait time = 16,384 states Wait time = 1,024 states Wait time = 2,048 states Wait time = 4,096 states Wait time = 2 states Wait time = 8 states Wait time = 16 states (External clock input mode) (initial value) Note: When inputting the external clock, set the standby timer select to the external clock input mode. Also, when not using the external clock, do not set the standby timer select to the external clock input mode. Bit 3: Low speed on flag (LSON) This bit chooses the system clock (o) or subclock (oSUB ) as the CPU operating clock when watch mode is cleared. The resulting operation mode depends on the combination of other control bits and interrupt input. Bit 3 LSON 0 1 Description The CPU operates on the system clock (o) The CPU operates on the subclock (o SUB) (initial value) Bit 2: Reserved bit Bit 2 is reserved: it is always read as 1 and cannot be modified. 99 Bits 1 and 0: Active (medium-speed) mode clock select (MA1, MA0) Bits 1 and 0 choose oOSC /128, oOSC /64, oOSC /32, or o OSC /16 as the operating clock in active (medium-speed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in active (high-speed) mode or subactive mode. Bit 1 MA1 0 0 1 1 Bit 0 MA0 0 1 0 1 Description oOSC/16 oOSC/32 oOSC/64 oOSC/128 (initial value) 2. System control register 2 (SYSCR2) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 NESEL 1 R/W 3 DTON 0 R/W 2 MSON 0 R/W 1 SA1 0 R/W 0 SA0 0 R/W SYSCR2 is an 8-bit read/write register for power-down mode control. Bits 7 to 5: Reserved bits These bits are reserved; they are always read as 1, and cannot be modified. Bit 4: Noise elimination sampling frequency select (NESEL) This bit selects the frequency at which the watch clock signal (oW) generated by the subclock pulse generator is sampled, in relation to the oscillator clock (oOSC) generated by the system clock pulse generator. When o OSC = 6 to 10 MHz, clear NESEL to 0. Bit 4 NESEL 0 1 Description Sampling rate is o OSC/16 Sampling rate is o OSC/4 (initial value) 100 Bit 3: Direct transfer on flag (DTON) This bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which the transition is made after the SLEEP instruction is executed depends on a combination of this and other control bits. Bit 3 DTON 0 Description * * 1 * When a SLEEP instruction is executed in active mode, a transition (initial value) is made to standby mode, watch mode, or sleep mode When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode When a SLEEP instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1 When a SLEEP instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1 When a SLEEP instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 1 * * Bit 2: Medium speed on flag (MSON) After standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active (medium-speed) mode. Bit 2 MSON 0 1 Description Operation in active (high-speed) mode Operation in active (medium-speed) mode (initial value) 101 Bits 1 and 0: Subactive mode clock select (SA1, SA0) These bits select the CPU clock rate (oW/2, oW /4, or o W /8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode. Bit 1 SA1 0 0 1 Bit 0 SA0 0 1 * Description oW/8 oW/4 oW/2 *: Don't care (initial value) 102 5.2 5.2.1 Sleep Mode Transition to Sleep Mode 1. Transition to sleep (high-speed) mode The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is executed while the SSBY and LSON bits in SYSCR1 are cleared to 0 and the MSON and DTON bits in SYSCR2 are also cleared to 0. In sleep mode CPU operation is halted but the on-chip peripheral functions. CPU register contents are retained. 2. Transition to sleep (medium-speed) mode The system goes from active mode to sleep (medium-speed) mode when a SLEEP instruction is executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is cleared to 0. In sleep (medium-speed) mode, as in sleep (high-speed) mode, CPU operation is halted but the on-chip peripheral functions are operational. The clock frequency in sleep (medium-speed) mode is determined by the MA1 and MA0 bits in SYSCR1. CPU register contents are retained. The CPU may operate at a 1/2 state faster timing at transition to sleep (medium-speed) mode. 5.2.2 Clearing Sleep Mode Sleep mode is cleared by any interrupt (timer A, timer C, timer F, timer G, asynchronous counter, IRQ4 to IRQ0, WKP7 to WKP0, SCI1, SCI31, SCI32, or A/D converter), or by input at the RES pin. * Clearing by interrupt When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. A transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep (medium-speed) mode to active (medium-speed) mode. Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the interrupt enable register. To synchronize the interrupt request signal with the system clock, up to 2/o (s) delay may occur after the interrupt request signal occurrence, before the interrupt exception handling start. * Clearing by RES input When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. 103 5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and MA0 bits in SYSCR1. 104 5.3 5.3.1 Standby Mode Transition to Standby Mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in TMA is cleared to 0. In standby mode the clock supply from the clock pulse generator is halted, so the CPU and peripheral modules other than the FLEXTM decoder stop functioning, but as long as the specified voltage is supplied, the contents of CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents will be further retained down to a minimum RAM data retention voltage. The I/O ports go to the high-impedance state. 5.3.2 Clearing Standby Mode Standby mode is cleared by an interrupt (IRQ1 or IRQ0), WKP 7 to WKP0 or by input at the RES pin. * Clearing by interrupt When an interrupt is requested, the system clock pulse generator starts. After the time set in bits STS2 to STS0 in SYSCR1 has elapsed, a stable system clock signal is supplied to the entire chip, standby mode is cleared, and interrupt exception handling starts. Operation resumes in active (high-speed) mode if MSON = 0 in SYSCR2, or active (medium-speed) mode if MSON = 1. Standby mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. * Clearing by RES input When the RES pin goes low, the system clock pulse generator starts. After the pulse generator output has stabilized, if the RES pin is driven high, the CPU starts reset exception handling. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin should be kept at the low level until the pulse generator output stabilizes. 5.3.3 Oscillator Settling Time after Standby Mode is Cleared Bits STS2 to STS0 in SYSCR1 should be set as follows. * When a crystal oscillator is used The table below gives settings for various operating frequencies. Set bits STS2 to STS0 for a waiting time at least as long as the oscillation settling time. 105 Table 5-4 STS2 0 0 0 0 1 1 1 1 Clock Frequency and Settling Time (times are in ms) STS1 0 0 1 1 0 0 1 1 STS0 0 1 0 1 0 1 0 1 Waiting Time 8,192 states 16,384 states 1,024 states 2,048 states 4,096 states 2 states (not available) 8 states 16 states 5 MHz 1.6384 3.2768 0.2048 0.4096 0.8192 0.0004 0.0016 0.0032 2 MHz 4.096 8.192 0.512 1.024 2.048 0.001 0.004 0.008 1 MHz 8.192 16.384 1.024 2.048 4.096 0.002 0.008 0.016 * When an external clock is used STS2 = 1, STS1 = 0 and STS0 = 1 are recommended. Other values can be set, but with other settings, operation may start before the standby time is over. 5.3.4 Standby Mode Transition and Pin States When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed) mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, and bit TMA3 is cleared to 0 in TMA, a transition is made to standby mode. At the same time, pins go to the highimpedance state (except pins for which the pull-up MOS is designated as on). Figure 5-2 shows the timing in this case. o Internal data bus SLEEP instruction fetch Fetch of next instruction Internal processing High-impedance Standby mode SLEEP instruction execution Pins Port output Active (high-speed) mode or active (medium-speed) mode Figure 5-2 Standby Mode Transition and Pin States 106 5.3.5 Notes on External Input Signal Changes before/after Standby Mode 1. When external input signal changes before/after standby mode or watch mode When an external input signal such as IRQ or WKP is input, both the high- and low-level widths of the signal must be at least two cycles of system clock o or subclock oSUB (referred to together in this section as the internal clock). As the internal clock stops in standby mode and watch mode, the width of external input signals requires careful attention when a transition is made via these operating modes. 2. When external input signals cannot be captured because internal clock stops The case of falling edge capture is illustrated in figure 5-3 As shown in the case marked "Capture not possible," when an external input signal falls immediately after a transition to active (high-speed or medium-speed) mode or subactive mode, after oscillation is started by an interrupt via a different signal, the external input signal cannot be captured if the high-level width at that point is less than 2 t cyc or 2 tsubcyc . 3. Recommended timing of external input signals To ensure dependable capture of an external input signal, high- and low-level signal widths of at least 2 tcyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch mode, as shown in "Capture possible: case 1." External input signal capture is also possible with the timing shown in "Capture possible: case 2" and "Capture possible: case 3," in which a 2 tcyc or 2 tsubcyc level width is secured. 107 Operating mode Active (high-speed, medium-speed) mode or subactive mode tcyc tsubcyc tcyc tsubcyc Wait for Active (high-speed, Standby mode oscillation medium-speed) mode or watch mode to settle or subactive mode tcyc tsubcyc tcyc tsubcyc o or oSUB External input signal Capture possible: case 1 Capture possible: case 2 Capture possible: case 3 Capture not possible Interrupt by different signall Figure 5-3 External Input Signal Capture when Signal Changes before/after Standby Mode or Watch Mode 4. Input pins to which these notes apply: IRQ4 to IRQ1, WKP7 to WKP0, ADTRG, TMIC, TMIF, TMIG 108 5.4 5.4.1 Watch Mode Transition to Watch Mode The system goes from active or subactive mode to watch mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1. In watch mode, operation of on-chip peripheral modules is halted except for timer A, timer F, timer G, and the FLEXTM decoder. As long as a minimum required voltage is applied, the contents of CPU registers, the on-chip RAM and some registers of the on-chip peripheral modules, are retained. I/O ports keep the same states as before the transition. 5.4.2 Clearing Watch Mode Watch mode is cleared by an interrupt (timer A, timer F, timer G, IRQ 0, or WKP7 to WKP0) or by input at the RES pin. * Clearing by interrupt When watch mode is cleared by interrupt, the mode to which a transition is made depends on the settings of LSON in SYSCR1 and MSON in SYSCR2. If both LSON and MSON are cleared to 0, transition is to active (high-speed) mode; if LSON = 0 and MSON = 1, transition is to active (medium-speed) mode; if LSON = 1, transition is to subactive mode. When the transition is to active mode, after the time set in SYSCR1 bits STS2 to STS0 has elapsed, a stable clock signal is supplied to the entire chip, watch mode is cleared, and interrupt exception handling starts. Watch mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. * Clearing by RES input Clearing by RES pin is the same as for standby mode; see 2. Clearing by RES pin in 5.3.2, Clearing Standby Mode. 5.4.3 Oscillator Settling Time after Watch Mode is Cleared The waiting time is the same as for standby mode; see 5.3.3, Oscillator Settling Time after Standby Mode is Cleared. 5.4.4 Notes on External Input Signal Changes before/after Watch Mode See 5.3.5, Notes on External Input Signal Changes before/after Standby Mode. 109 5.5 5.5.1 Subsleep Mode Transition to Subsleep Mode The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than the A/D converter and WDT is halted. As long as a minimum required voltage is applied, the contents of CPU registers, the on-chip RAM and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states as before the transition. 5.5.2 Clearing Subsleep Mode Subsleep mode is cleared by an interrupt (timer A, timer C, timer F, timer G, SCI1, SCI32, SCI31, IRQ4 to IRQ0, WKP7 to WKP0) or by a low input at the RES pin. * Clearing by interrupt When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. To synchronize the interrupt request signal with the subclock, up to 2/oSUB (s) delay may occur after the interrupt request signal occurrence, before the interrupt exception handling start. * Clearing by RES input Clearing by RES pin is the same as for standby mode; see 2. Clearing by RES pin in 5.3.2, Clearing Standby Mode. 110 5.6 5.6.1 Subactive Mode Transition to Subactive Mode Subactive mode is entered from watch mode if a timer A, timer F, timer G, IRQ0, or WKP7 to WKP0 interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A, timer C, timer F, timer G, SCI1, SCI31, SCI32, IRQ 4 to IRQ0, or WKP7 to WKP0 interrupt is requested. A transition to subactive mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. 5.6.2 Clearing Subactive Mode Subactive mode is cleared by a SLEEP instruction or by a low input at the RES pin. * Clearing by SLEEP instruction If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in TMA is set to 1, subactive mode is cleared and watch mode is entered. If a SLEEP instruction is executed while SSBY = 0 and LSON = 1 in SYSCR1 and TMA3 = 1 in TMA, subsleep mode is entered. Direct transfer to active mode is also possible; see 5.8, Direct Transfer, below. * Clearing by RES pin Clearing by RES pin is the same as for standby mode; see 2. Clearing by RES pin in 5.3.2, Clearing Standby Mode. 5.6.3 Operating Frequency in Subactive Mode The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices are oW /2, oW /4, and oW /8. 111 5.7 5.7.1 Active (Medium-Speed) Mode Transition to Active (Medium-Speed) Mode If the RES pin is driven low, active (medium-speed) mode is entered. If the LSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed) mode results from IRQ0, IRQ1 or WKP7 to WKP0 interrupts in standby mode, timer A, timer F, timer G, IRQ0 or WKP 7 to WKP0 interrupts in watch mode, or any interrupt in sleep mode. A transition to active (medium-speed) mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. The CPU may operate at a 1/2 state faster timing at transition to active (medium-speed) mode. 5.7.2 Clearing Active (Medium-Speed) Mode Active (medium-speed) mode is cleared by a SLEEP instruction. * Clearing by SLEEP instruction A transition to standby mode takes place if the SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and the TMA3 bit in TMA is cleared to 0. The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1 when a SLEEP instruction is executed. When both SSBY and LSON are cleared to 0 in SYSCR1 and a SLEEP instruction is executed, sleep mode is entered. Direct transfer to active (high-speed) mode or to subactive mode is also possible. See 5.8, Direct Transfer, below for details. * Clearing by RES pin When the RES pin is driven low, a transition is made to the reset state and active (medium-speed) mode is cleared. 5.7.3 Operating Frequency in Active (Medium-Speed) Mode Operation in active (medium-speed) mode is clocked at the frequency designated by the MA1 and MA0 bits in SYSCR1. 112 5.8 5.8.1 Direct Transfer Overview of Direct Transfer The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution. A direct transfer can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. After the mode transition, direct transfer interrupt exception handling starts. If the direct transfer interrupt is disabled in interrupt enable register 2, a transition is made instead to sleep mode or watch mode. Note that if a direct transition is attempted while the I bit in CCR is set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear the resulting mode by means of an interrupt. * Direct transfer from active (high-speed) mode to active (medium-speed) mode When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (medium-speed) mode via medium-speed sleep mode. * Direct transfer from active (medium-speed) mode to active (high-speed) mode When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via high-speed sleep mode. * Direct transfer from active (high-speed) mode to subactive mode When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode. * Direct transfer from subactive mode to active (high-speed) mode When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made directly to active (high-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed. 113 * Direct transfer from active (medium-speed) mode to subactive mode When a SLEEP instruction is executed in active (medium-speed) while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode. * Direct transfer from subactive mode to active (medium-speed) mode When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed. 5.8.2 Direct Transition Times 1. Time for direct transition from active (high-speed) mode to active (medium-speed) mode A direct transition from active (high-speed) mode to active (medium-speed) mode is performed by executing a SLEEP instruction in active (high-speed) mode while bits SSBY and LSON are both cleared to 0 in SYSCR1, and bits MSON and DTON are both set to 1 in SYSCR2. The time from execution of the SLEEP instruction to the end of interrupt exception handling (the direct transition time) is given by equation (1) below. Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal processing states) } x (tcyc before transition) + (number of interrupt exception handling execution states) x (tcyc after transition) .................................. (1) Example: Direct transition time = (2 + 1) x 2tosc + 14 x 16tosc = 230tosc (when o/8 is selected as the CPU operating clock) Notation: tosc: OSC clock cycle time tcyc: System clock (o) cycle time 2. Time for direct transition from active (medium-speed) mode to active (high-speed) mode A direct transition from active (medium-speed) mode to active (high-speed) mode is performed by executing a SLEEP instruction in active (medium-speed) mode while bits SSBY and LSON are both cleared to 0 in SYSCR1, and bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2. The time from execution of the SLEEP instruction to the end of interrupt exception handling (the direct transition time) is given by equation (2) below. 114 Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal processing states) } x (tcyc before transition) + (number of interrupt exception handling execution states) x (tcyc after transition) .................................. (2) Example: Direct transition time = (2 + 1) x 16tosc + 14 x 2tosc = 76tosc (when o/8 is selected as the CPU operating clock) Notation: tosc: OSC clock cycle time tcyc: System clock (o) cycle time 3. Time for direct transition from subactive mode to active (high-speed) mode A direct transition from subactive mode to active (high-speed) mode is performed by executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2, and bit TMA3 is set to 1 in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception handling (the direct transition time) is given by equation (3) below. Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal processing states) } x (tsubcyc before transition) + { (wait time set in STS2 to STS0) + (number of interrupt exception handling execution states) } x (tcyc after transition) ........................ (3) Example: Direct transition time = (2 + 1) x 8tw + (8192 + 14) x 2tosc= 24tw + 16412tosc (when ow/8 is selected as the CPU operating clock, and wait time = 8192 states) Notation: tosc: tw: tcyc: tsubcyc : OSC clock cycle time Watch clock cycle time System clock (o) cycle time Subclock (oSUB) cycle time 115 4. Time for direct transition from subactive mode to active (medium-speed) mode A direct transition from subactive mode to active (medium-speed) mode is performed by executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, bits MSON and DTON are both set to 1 in SYSCR2, and bit TMA3 is set to 1 in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception handling (the direct transition time) is given by equation (4) below. Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal processing states) } x (tsubcyc before transition) + { (wait time set in STS2 to STS0) + (number of interrupt exception handling execution states) } x (tcyc after transition) ........................ (4) Example: Direct transition time = (2 + 1) x 8tw + (8192 + 14) x 16tosc= 24tw + 131296tosc (when ow/8 or o8 is selected as the CPU operating clock, and wait time = 8192 states) Notation: tosc: tw: tcyc: tsubcyc : 5.8.3 OSC clock cycle time Watch clock cycle time System clock (o) cycle time Subclock (oSUB) cycle time Notes on External Input Signal Changes before/after Direct Transition 1. Direct transition from active (high-speed) mode to subactive mode Since the mode transition is performed via watch mode, see 5.3.5, Notes on External Input Signal Changes before/after Standby Mode. 2. Direct transition from active (medium-speed) mode to subactive mode Since the mode transition is performed via watch mode, see 5.3.5, Notes on External Input Signal Changes before/after Standby Mode. 3. Direct transition from subactive mode to active (high-speed) mode Since the mode transition is performed via watch mode, see 5.3.5, Notes on External Input Signal Changes before/after Standby Mode. 4. Direct transition from subactive mode to active (medium-speed) mode Since the mode transition is performed via watch mode, see 5.3.5, Notes on External Input Signal Changes before/after Standby Mode. 116 5.9 5.9.1 Module Standby Mode Setting Module Standby Mode Module standby mode is set for individual peripheral functions. All the on-chip peripheral modules can be placed in module standby mode. When a module enters module standby mode, the system clock supply to the module is stopped and operation of the module halts. This state is identical to standby mode. Module standby mode is set for a particular module by setting the corresponding bit to 0 in clock stop register 1 (CKSTPR1) or clock stop register 2 (CKSTPR2). (See table 5-5.) 5.9.2 Clearing Module Standby Mode Module standby mode is cleared for a particular module by setting the corresponding bit to 1 in clock stop register 1 (CKSTPR1) or clock stop register 2 (CKSTPR2). (See table 5-5.) Following a reset, clock stop register 1 (CKSTPR1) and clock stop register 2 (CKSTPR2) are both initialized to H'FF. 117 Table 5-5 Setting and Clearing Module Standby Mode by Clock Stop Register Bit Name TACKSTP 1 0 TCCKSTP 1 0 TFCKSTP 1 0 TGCKSTP 1 0 ADCKSTP 1 0 S1CKSTP 1 0 S32CKSTP 1 0 S31CKSTP 1 0 Operation Timer A module standby mode is cleared Timer A is set to module standby mode Timer C module standby mode is cleared Timer C is set to module standby mode Timer F module standby mode is cleared Timer F is set to module standby mode Timer G module standby mode is cleared Timer G is set to module standby mode A/D converter module standby mode is cleared A/D converter is set to module standby mode SCI1 module standby mode is cleared SCI1 is set to module standby mode SCI32 module standby mode is cleared SCI32 is set to module standby mode SCI31 module standby mode is cleared SCI31 is set to module standby mode Register Name CKSTPR1 Table 5-5 Setting and Clearing Module Standby Mode by Clock Stop Register (cont) Bit Name WDCKSTP 1 0 Operation Watchdog timer module standby mode is cleared Watchdog timer is set to module standby mode Register Name CKSTPR2 Note: For details of module operation, see the sections on the individual modules. 118 Section 6 ROM 6.1 Overview The H8/3935 and H8/3935R have 40 kbytes of mask ROM, the H8/3936 and H8/3936R have 48 kbytes of mask ROM, and the H8/3937 and H8/3937R have 60 kbytes of mask ROM on-chip. The ROM is connected to the CPU by a 16-bit data bus, allowing high-speed two-state access for both byte data and word data. The H8/3937 and H8/3937R have a ZTATTM version with 60-kbyte PROM. 6.1.1 Block Diagram Figure 6-1 shows a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'0000 H'0002 H'0000 H'0002 H'0001 H'0003 On-chip ROM H'9FFE H'9FFE Even-numbered address H'9FFF Odd-numbered address Figure 6-1 ROM Block Diagram (H8/3935, H8/3935R) 119 6.2 6.2.1 PROM Mode Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as the standard HN27C101 EPROM. However, page programming is not supported. Table 6-1 shows how to set the chip to PROM mode. Table 6-1 Pin Name TEST P90, PB4/AN4 P91, PB5/AN5 P92, PB6/AN6 High level Setting to PROM Mode Setting High level Low level 6.2.2 Socket Adapter Pin Arrangement and Memory Map A standard PROM programmer can be used to program the PROM. A socket adapter is required for conversion to 32 pins, as listed in table 6-2. Figure 6-2 shows the pin-to-pin wiring of the socket adapter. Figure 6-3 shows a memory map. Table 6-2 Package 100-pin (TFP-100B) Socket Adapter Socket Adapter Model (Manufacturer) H7393BT100D3201 (DATA-I/O) ME3937ESNSIH (MINATO) 100-pin (TFP-100G) H7393GT100D3201 (DATA-I/O) ME3937ESMSIH (MINATO) 120 H8/3937, H8/3937R TFP-100B, TFP-100G 13 43 44 45 46 47 48 49 50 94 93 92 91 90 89 88 87 53 34 55 56 57 58 59 18 19 60 54 17 12, 52 99 86 85 97 15 16 20 6 11, 51 8 95 96 83 72 71 70 4 5 81 Pin RES P60 P61 P62 P63 P64 P65 P66 P67 P87 P86 P85 P84 P83 P82 P81 P80 P70 TESTA9H P72 P73 P74 P75 P76 P14 P15 P77 P71 P13 VCC AVCC TEST DX1 P92 P11 P12 P16 PB6 VSS AVSS P90 P91 TESTD EXS0 EXS1 LOBAT PB4 PB5 SO EPROM socket Pin VPP EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 EA16 CE OE PGM VCC HN27C101 (32-pin) 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32 VSS 16 Note: Pins not indicated in the figure should be left open. Figure 6-2 Socket Adapter Pin Correspondence (with HN27C101) 121 Address in MCU mode H'0000 Address in PROM mode H'0000 On-chip PROM H'EDFF Uninstalled area* H'EDFF H'1FFFF Note: * The output data is not guaranteed if this address area is read in PROM mode. Therefore, when programming with a PROM programmer, be sure to specify addresses from H'0000 to H'EDFF. If programming is inadvertently performed from H'EE00 onward, it may not be possible to continue PROM programming and verification. When programming, H'FF should be set as the data in this address area (H'EE00 to H'1FFFF). Figure 6-3 H8/3937 and H8/3937R Memory Map in PROM Mode 122 6.3 Programming The write, verify, and other modes are selected as shown in table 6-3 in PROM mode. Table 6-3 Mode Selection in PROM Mode (H8/3937, H8/3937R) Pins Mode Write Verify Programming disabled CE L L L L H H Notation: L: Low level H: High level VPP level VPP : VCC level VCC: OE H L L H L H PGM L H L H L H VPP VPP VPP VPP VCC VCC VCC VCC EO7 to EO0 Data input Data output High i pedanc e m EA 16 to EA0 Address input Address input Address input The specifications for writing and reading are identical to those for the standard HN27C101 EPROM. However, page programming is not supported, and so page programming mode must not be set. A PROM programmer that only supports page programming mode cannot be used. When selecting a PROM programmer, ensure that it supports high-speed, high-reliability byte-by-byte programming. Also, be sure to specify addresses from H'0000 to H'EDFF. 6.3.1 Writing and Verifying An efficient, high-speed, high-reliability method is available for writing and verifying the PROM data. This method achieves high speed without voltage stress on the device and without lowering the reliability of written data. The basic flow of this high-speed, high-reliability programming method is shown in figure 6-4. 123 Start Set write/verify mode VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V Address = 0 n=0 n+1 n No Yes n < 25 Write time t PW = 0.2 ms 5% No Go Verify Go Address + 1 address Write time t OPW = 3n ms No Last address? Yes Set read mode VCC = 5.0 V 0.25 V, V PP = VCC No Go Error Read all addresses? Go End Figure 6-4 High-Speed, High-Reliability Programming Flow Chart 124 Table 6-4 and table 6-5 give the electrical characteristics in programming mode. Table 6-4 DC Characteristics (Conditions: VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Symbol Min 2.4 -0.3 2.4 -- -- -- -- Typ -- -- -- -- -- -- -- Max Unit Test Condi ti on Input highEO7 to EO 0, EA16 to EA 0 VIH level voltage OE, CE, PGM Input lowEO7 to EO 0, EA16 to EA 0 VIL level voltage OE, CE, PGM Output high- EO7 to EO 0 level voltage Output low EO7 to EO 0 level voltage VOH VOL VCC + 0.3 V 0.8 -- 0.45 2 40 40 V V V A mA mA I OH = -200 A I OL = 0.8 mA Vin = 5.25 V/0.5 V Input leakage EO7 to EO 0, EA16 to EA 0 |ILI| current OE, CE, PGM VCC current VPP current I CC I PP 125 Table 6-5 AC Characteristics (Conditions: VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C) Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time VPP setup time Programming pulse width PGM pulse width for overwrite programming CE setup time VCC setup time Data output delay time Symbol t AS t OES t DS t AH t DH t DF * t VPS t PW t OPW* t CES t VCS t OE 3 2 Min 2 2 2 0 2 -- 2 0.19 0.19 2 2 0 Typ -- -- -- -- -- -- -- 0.20 -- -- -- -- Max -- -- -- -- -- 130 -- 0.21 5.25 -- -- 200 Unit Test Condition s s s s s s s ms ms s s ns Figure 6-5* 1 Notes: 1. Input pulse level: 0.45 V to 2.4 V Input rise time/fall time 20 ns Timing reference levels Input: 0.8 V, 2.0 V Output: 0.8 V, 2.0 V 2. t DF is defined at the point at which the output is floating and the output level cannot be read. 3. t OPW is defined by the value given in figure 6-4, High-Speed, High-Reliability Programming Flow Chart. 126 Figure 6-5 shows a PROM write/verify timing diagram. Write Address Verify tAS Data tDS VPP VPP VCC tVPS Input data tDH Output data tAH tDF VCC VCC+1 VCC tVCS CE tCES PGM tPW OE tOPW* tOES tOE Note: * topw is defined by the value shown in figure 6.4, High-Speed, High-Reliability Programming Flowchart. Figure 6-5 PROM Write/Verify Timing 127 6.3.2 Programming Precautions * Use the specified programming voltage and timing. * The programming voltage in PROM mode (VPP) is 12.5 V. Use of a higher voltage can permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Hitachi specifications for the HN27C101 will result in correct VPP of 12.5 V. * Make sure the index marks on the PROM programmer socket, socket adapter, and chip are properly aligned. If they are not, the chip may be destroyed by excessive current flow. Before programming, be sure that the chip is properly mounted in the PROM programmer. * Avoid touching the socket adapter or chip while programming, since this may cause contact faults and write errors. * Take care when setting the programming mode, as page programming is not supported. * When programming with a PROM programmer, be sure to specify addresses from H'0000 to H'EDFF. If programming is inadvertently performed from H'EE00 onward, it may not be possible to continue PROM programming and verification. When programming, H'FF should be set as the data in address area H'EE00 to H'1FFFF. 128 6.4 Reliability of Programmed Data A highly effective way to improve data retention characteristics is to bake the programmed chips at 150C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to early failure. Figure 6-6 Shows the recommended screening procedure. Program chip and verify programmed data Bake chip for 24 to 48 hours at 125C to 150C with power off Read and check program Install Figure 6-6 Recommended Screening Procedure If a series of programming errors occurs while the same PROM programmer is in use, stop programming and check the PROM programmer and socket adapter for defects. Please inform Hitachi of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking. 129 130 Section 7 RAM 7.1 Overview The H8/3937 Series and H8/3937R Series have 2 kbytes of high-speed static RAM on-chip. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. 7.1.1 Block Diagram Figure 7-1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'F780 H'F782 H'F780 H'F782 H'F781 H'F783 On-chip RAM H'FF7E H'FF7E Even-numbered address H'FF7F Odd-numbered address Figure 7-1 RAM Block Diagram (H8/3935, H8/3935R) 131 132 Section 8 I/O Ports 8.1 Overview The H8/3937 Series and H8/3937R Series are provided with six 8-bit I/O ports, two 4-bit I/O ports, one 3-bit I/O port, and one 8-bit input-only port. Also provided are one internal 5-bit I/O port and one internal 1-bit input-only port capable of interfacing to the on-chip FLEXTM decoder. Table 8-1 indicates the functions of each port. Each port has of a port control register (PCR) that controls input and output, and a port data register (PDR) for storing output data. Input or output can be assigned to individual bits. See 2.9.2, Notes on Bit Manipulation, for information on executing bit-manipulation instructions to write data in PCR or PDR. Block diagrams of each port are given in Appendix C, I/O Port Block Diagrams Table 8-1 Port Functions Pins and Functions Function Switching Registers PMR1 TCRF, TMC PMR1, AMR PMR1 PMR1 PMR1 PMR2 Port Port 1 Description * * Other Functions 8-bit I/O port P17 to P1 5/IRQ3 to External interrupts 3 to 1 MOS input pull-up option IRQ1/TMIF, TMIC Timer event interrupts TMIF, TMIC P14/IRQ4/ADTRG External interrupt 4 and A/D converter external trigger P13/TMIG Timer G input capture input P12, P11/ Timer F output compare TMOFH, TMOFL output P10/TMOW Port 2* * 1 Timer A clock output SCI1 data output (SO1), data input (SI 1), clock input/output (SCK1) None 5-bit I/O internal port P20/SCK1 P21/SI1 P22/SO 1 P24, P23 133 Port Port 3 Description * * Pins and Functions Other Functions SCI31 data output (TXD31 ), data input (RXD31 ), clock input/output (SCK31 ) Function Switching Registers PMR3 SCR31 SMR31 8-bit I/O port P37 MOS input pull-up option P36 P35/TXD31 P34/RXD31 P33/SCK31 P32/RESO P31/UD P30 Reset output, timer C countup/down select input Internal IRQ interrupt 0 SCI32 data output (TXD32 ), data input (RXD32 ), clock input/output (SCK32 ) Wakeup input (WKP 7 to WKP 0) PMR3 Port 4 * * 1-bit input internal port 3-bit I/O port P43/IRQ0* 2 P42/TXD32 P41/RXD32 P40/SCK32 PMR3 SCR32 SMR32 PMR5 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B * * * * * * * * * 8-bit I/O port P57 to P5 0/ MOS input pull-up option WKP 7 to WKP 0 8-bit I/O port P67 to P6 0 MOS input pull-up option 8-bit I/O port P77 to P7 0 8-bit I/O port 4-bit I/O port 4-bit I/O port 8-bit input port P87 to P8 0 P93 to P9 0 PA3 to PA 0 PB7 to PB 0/ AN 7 to AN0 A/D converter analog input AMR Notes: 1. Internal I/O port for interfacing to the FLEXTM decoder. 2. Internal input port for interfacing to the FLEXTM decoder. 134 8.2 8.2.1 Port 1 Overview Port 1 is an 8-bit I/O port. Figure 8-1 shows its pin configuration. P1 7 /IRQ 3 /TMIF P1 6 /IRQ 2 P1 5 /IRQ 1 /TMIC Port 1 P1 4 /IRQ 4 /ADTRG P1 3 /TMIG P1 2 /TMOFH P1 1 /TMOFL P1 0 /TMOW Figure 8-1 Port 1 Pin Configuration 8.2.2 Register Configuration and Description Table 8-2 shows the port 1 register configuration. Table 8-2 Name Port data register 1 Port control register 1 Port pull-up control register 1 Port mode register 1 Port 1 Registers Abbrev. PDR1 PCR1 PUCR1 PMR1 R/W R/W W R/W R/W Initial Value H'00 H'00 H'00 H'00 Address H'FFD4 H'FFE4 H'FFE0 H'FFC8 135 1. Port data register 1 (PDR1) Bit Initial value Read/Write 7 P1 7 0 R/W 6 P1 6 0 R/W 5 P1 5 0 R/W 4 P1 4 0 R/W 3 P1 3 0 R/W 2 P1 2 0 R/W 1 P1 1 0 R/W 0 P1 0 0 R/W PDR1 is an 8-bit register that stores data for port 1 pins P17 to P10. If port 1 is read while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If port 1 is read while PCR1 bits are cleared to 0, the pin states are read. Upon reset, PDR1 is initialized to H'00. 2. Port control register 1 (PCR1) Bit Initial value Read/Write 7 PCR17 0 W 6 PCR16 0 W 5 PCR15 0 W 4 PCR14 0 W 3 PCR13 0 W 2 PCR12 0 W 1 PCR11 0 W 0 PCR10 0 W PCR1 is an 8-bit register for controlling whether each of the port 1 pins P17 to P10 functions as an input pin or output pin. Setting a PCR1 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR1 and in PDR1 are valid only when the corresponding pin is designated in PMR1 as a general I/O pin. Upon reset, PCR1 is initialized to H'00. PCR1 is a write-only register, which is always read as all 1s. 3. Port pull-up control register 1 (PUCR1) Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10 PUCR1 controls whether the MOS pull-up of each of the port 1 pins P17 to P10 is on or off. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR1 is initialized to H'00. 136 4. Port mode register 1 (PMR1) Bit Initial value Read/Write 7 IRQ3 0 R/W 6 IRQ2 0 R/W 5 IRQ1 0 R/W 4 IRQ4 0 R/W 3 TMIG 0 R/W 2 TMOFH 0 R/W 1 TMOFL 0 R/W 0 TMOW 0 R/W PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. Upon reset, PMR1 is initialized to H'00. Bit 7: P17/IRQ3/TMIF pin function switch (IRQ3) This bit selects whether pin P17/IRQ3/TMIF is used as P1 7 or as IRQ3/TMIF. Bit 7 IRQ3 0 1 Description Functions as P1 7 I/O pin Functions as IRQ3/TMIF input pin (initial value) Note: Rising or falling edge sensing can be designated for IRQ3/TMIF. For details on TMIF settings, see 3. Timer Control Register F (TCRF) in 9.4.2. Bit 6: P16/IRQ2 pin function switch (IRQ2) This bit selects whether pin P16/IRQ2 is used as P16 or as IRQ2. Bit 6 IRQ2 0 1 Description Functions as P1 6 I/O pin Functions as IRQ2 input pin (initial value) Note: Rising or falling edge sensing can be designated for IRQ2. Bit 5: P15/IRQ1/TMIC pin function switch (IRQ1) This bit selects whether pin P15/IRQ1/TMIC is used as P15 or as IRQ1/TMIC. Bit 5 IRQ1 0 1 Description Functions as P1 5 I/O pin Functions as IRQ1/TMIC input pin (initial value) Note: Rising or falling edge sensing can be designated for IRQ1/TMIC. For details of TMIC pin setting, see 1. Timer mode register C (TMC) in 9.3.2. 137 Bit 4: P14/IRQ4/ADTRG pin function switch (IRQ4) This bit selects whether pin P14/IRQ4/ADTRG is used as P14 or as IRQ4/ADTRG. Bit 4 IRQ4 0 1 Description Functions as P1 4 I/O pin Functions as IRQ4/ADTRG input pin (initial value) Note: For details of ADTRG pin setting, see 12.3.2, Start of A/D Conversion by External Trigger. Bit 3: P13/TMIG pin function switch (TMIG) This bit selects whether pin P13/TMIG is used as P13 or as TMIG. Bit 3 TMIG 0 1 Description Functions as P1 3 I/O pin Functions as TMIG input pin (initial value) Bit 2: P12/TMOFH pin function switch (TMOFH) This bit selects whether pin P12/TMOFH is used as P12 or as TMOFH. Bit 2 TMOFH 0 1 Description Functions as P1 2 I/O pin Functions as TMOFH output pin (initial value) Bit 1: P11/TMOFL pin function switch (TMOFL) This bit selects whether pin P11/TMOFL is used as P1 1 or as TMOFL. Bit 1 TMOFL 0 1 Description Functions as P1 1 I/O pin Functions as TMOFL output pin (initial value) 138 Bit 0: P10/TMOW pin function switch (TMOW) This bit selects whether pin P10/TMOW is used as P10 or as TMOW. Bit 0 TMOW 0 1 Description Functions as P1 0 I/O pin Functions as TMOW output pin (initial value) 139 8.2.3 Pin Functions Table 8-3 shows the port 1 pin functions. Table 8-3 Pin P17/IRQ3/TMIF Port 1 Pin Functions Pin Functions and Selection Method The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF, and bit PCR1 7 in PCR1. IRQ3 PCR17 CKSL2 to CKSL0 Pin function 0 0 * P17 input pin 1 1 * 0** IRQ3/TMIF input pin Not 0** P17 output pin IRQ3 input pin Note: When this pin is used as the TMIF input pin, clear bit IEN3 to 0 in IENR1 to disable the IRQ3 interrupt. P16/IRQ2 The pin function depends on bits IRQ2 in PMR1 and bit PCR1 6 in PCR1. IRQ2 PCR16 Pin function P15/IRQ1 TMIC 0 0 P16 input pin 1 P16 output pin 1 * IRQ2 input pin The pin function depends on bit IRQ1 in PMR1, bits TMC2 to TMC0 in TMC, and bit PCR15 in PCR1. IRQ1 PCR15 TMC2 to TMC0 Pin function 0 0 * P15 input pin 1 1 * 111 IRQ1/TMIC input pin Not 111 P15 output pin IRQ1 input pin Note: When this pin is used as the TMIC input pin, clear bit IEN1 to 0 in IENR1 to disable the IRQ1 interrupt. P14/IRQ4 ADTRG The pin function depends on bit IRQ4 in PMR1, bit TRGE in AMR, and bit PCR1 4 in PCR1. IRQ4 PCR14 TRGE Pin function 0 0 * P14 input pin 1 1 * 0 1 P14 output pin IRQ4 input pin IRQ4/ADTRG input pin Note: When this pin is used as the ADTRG input pin, clear bit IEN4 to 0 in IENR1 to disable the IRQ4 interrupt. 140 Pin P13/TMIG Pin Functions and Selection Method The pin function depends on bit TMIG in PMR1 and bit PCR13 in PCR1. TMIG PCR13 Pin function 0 0 P13 input pin 1 P13 output pin 1 * TMIG input pin P12/TMOFH The pin function depends on bit TMOFH in PMR1 and bit PCR12 in PCR1. TMOFH PCR12 Pin function 0 0 P12 input pin 1 P12 output pin 1 * TMOFH output pin P11/TMOFL The pin function depends on bit TMOFL in PMR1 and bit PCR1 1 in PCR1. TMOFL PCR11 Pin function 0 0 P11 input pin 1 P11 output pin 1 * TMOFL output pin P10/TMOW The pin function depends on bit TMOW in PMR1 and bit PCR1 0 in PCR1. TMOW PCR10 Pin function 0 0 P10 input pin 1 P10 output pin 1 * TMOW output pin *: Don't care 141 8.2.4 Pin States Table 8-4 shows the port 1 pin states in each operating mode. Table 8-4 Pins P17/IRQ3/TMIF P16/IRQ2 P15/IRQ1/TMIC P14/IRQ4/ADTRG P13/TMIG P12/TMOFH P11/TMOFL P10/TMOW Port 1 Pin States Reset Sleep Subsleep Retains previous state Standby Watch Subactive Functional Active Functional HighRetains impedance previous state HighRetains impedance* previous state Note: * A high-level signal is output when the MOS pull-up is in the on state. 8.2.5 MOS Input Pull-Up Port 1 has a built-in MOS input pull-up function that can be controlled by software. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset. PCR1n PUCR1n MOS input pull-up 0 0 Off 0 1 On 1 * Off (n = 7 to 0) *: Don't care 142 8.3 8.3.1 Port 2 [Chip Internal I/O Port] Overview Port 2 is a 5-bit I/O internal port. Figure 8-2 shows its functional configuration. Port 2 is an internal function that performs interfacing to the FLEXTM decoder incorporated in the chip. It cannot be connected to an IC outside the chip. P24 P23 Port 2 P22/SO1 P21/SI1 P20/SCK1 RESET SS MOSI MISO SCK FLEXTM decoder Note: : Connected inside the chip. Figure 8-2 Port 2 Functional Configuration 8.3.2 Register Configuration and Description Table 8-5 shows the port 2 register configuration. Table 8-5 Name Port data register 2 Port control register 2 Port mode register 2 Port mode register 4 Port 2 Registers Abbrev. PDR2 PCR2 PMR2 PMR4 R/W R/W W R/W R/W Initial Value H'00 H'00 H'D8 H'00 Address H'FFD5 H'FFE5 H'FFC9 H'FFCB 143 1. Port data register 2 (PDR2) Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 P24 0 R/W 3 P23 0 R/W 2 P22 0 R/W 1 P21 0 R/W 0 P20 0 R/W PDR2 is an 8-bit register that stores data for port 2 pins P24 to P20. If port 2 is read while PCR2 bits are set to 1, the values stored in PDR2 are read directly. Do not read port 2 while PCR2 bits are cleared to 0. Upon reset, PDR2 is initialized to H'00. 2. Port control register 2 (PCR2) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 PCR24 0 W 3 PCR23 0 W 2 PCR22 0 W 1 PCR21 0 W 0 PCR20 0 W PCR2 is an 8-bit register for controlling whether each of port 2 pins P24 to P20 functions as an input pin or output pin. Setting a PCR2 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR2 and PDR2 are valid only when the corresponding pin is designated in PMR2 as a general I/O pin. Upon reset, PCR2 is initialized to H'00. PCR2 is a write-only register, which is always read as all 1s. 3. Port mode register 2 (PMR2) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 POF1 0 R/W 4 -- 1 -- 3 -- 1 -- 2 SO1 0 R/W 1 SI1 0 R/W 0 SCK1 0 R/W PMR2 is an 8-bit read/write register that controls the selection of pin functions for port 2 pins P20, P2 1, and P22, and the PMOS on/off state for the P22/SO 1 pin. Bit 5, the P22/SO 1 pin PMOS control bit (POF1), should be cleared to 0. Upon reset, PMR2 is initialized to H'D8. 144 Bits 7, 6, 4, and 3: Reserved bits Bits 7, 6, 4, and 3 are reserved; they are always read as 1 and cannot be modified. Bit 5: P22/SO 1 pin PMOS control (POF1) This bit controls the on/off state of the P2 2/SO 1 pin PMOS. This bit should be cleared to 0. Bit 5 POF1 0 1 Description CMOS setting NMOS open-drain setting (initial value) Bit 2: P22/SO 1 pin function switch (SO1) This bit selects whether pin P22/SO 1 is used as P22 or as SO1. Bit 2 SO1 0 1 Description Functions as P2 2 I/O pin Functions as SO 1 output pin (initial value) Bit 1: P2 1/SI 1 pin function switch (SI1) This bit selects whether pin P21/SI1 is used as P21 or as SI1. Bit 1 SI1 0 1 Description Functions as P2 1 I/O pin Functions as SI1 input pin (initial value) Bit 0: P2 0/SCK1 pin function switch (SCK1) This bit selects whether pin P20/SCK1 is used as P20 or as SCK 1. Bit 0 SCK1 0 1 Description Functions as P2 0 I/O pin Functions as SCK1 I/O pin (initial value) 145 4. Port mode register 4 (PMR4) Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W NMOD4 NMOD3 NMOD2 NMOD1 NMOD0 PMR4 is an 8-bit read/write register that controls whether individual port 2 pins are set as CMOS or NMOS open-drain when 1 is set in PCR. A 0 setting should be used for this function. Upon reset, PMR4 is initialized to H'00. Bit n: NMOS open-drain output select (NMODn) These bits select NMOS open-drain when pin P2n is used as an output pin. These bits should be cleared to 0. Bit n NMODn 0 1 Description CMOS setting NMOS open-drain setting (n = 4 to 0) (initial value) 146 8.3.3 Function Table 8-6 shows the port 2 functions. Table 8-6 Functions P24, P23 Port 2 Functions Functions and Selection Method The function depends on the corresponding bit in PCR2. (n = 4 or 3) PCR2n Function 0 P2n input 1 P2n output P22/SO 1 The function depends on bit SO1 in PMR2 and bit PCR2 2 in PCR2. SO1 PCR22 Function 0 0 P22 input 1 P22 output 1 * SO1 output P21/SI1 The function depends on bit SI1 in PMR2 and bit PCR21 in PCR2. SI1 PCR21 Function 0 0 P21 input 1 P21 output 1 * SI 1 input P20/SCK1 The function depends on bit SCK1 in PMR2 and bit PCR20 in PCR2. SCK1 PCR20 Function 0 0 P20 input 1 P20 output 1 * SCK 1 I/O *: Don't care 8.3.4 States Table 8-7 shows the port 2 states in each operating mode. Table 8-7 Functions P24 P23 P22/SO1 P21/SI1 P20/SCK 1 Port 2 States Reset Low High Low Sleep Retains previous state Subsleep Retains previous state Standby Retains previous state Watch Retains previous state Subactive Functional Active Functional 147 8.4 8.4.1 Port 3 Overview Port 3 is an 8-bit I/O port, configured as shown in figure 8-3. P3 7 P3 6 P3 5 /TXD31 Port 3 P3 4 /RXD31 P3 3 /SCK 31 P3 2 /RESO P3 1 /UD P3 0 Figure 8-3 Port 3 Pin Configuration 8.4.2 Register Configuration and Description Table 8-8 shows the port 3 register configuration. Table 8-8 Name Port data register 3 Port control register 3 Port pull-up control register 3 Port mode register 3 Port 3 Registers Abbrev. PDR3 PCR3 PUCR3 PMR3 R/W R/W W R/W R/W Initial Value H'00 H'00 H'00 H'04 Address H'FFD6 H'FFE6 H'FFE1 H'FFCA 148 1. Port data register 3 (PDR3) Bit Initial value Read/Write 7 P3 7 0 R/W 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W 3 P3 3 0 R/W 2 P32 0 R/W 1 P31 0 R/W 0 P3 0 0 R/W PDR3 is an 8-bit register that stores data for port 3 pins P37 to P30. If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read. Upon reset, PDR3 is initialized to H'00. 2. Port control register 3 (PCR3) Bit Initial value Read/Write 7 PCR3 7 0 W 6 PCR3 6 0 W 5 PCR3 5 0 W 4 PCR34 0 W 3 PCR3 3 0 W 2 PCR3 2 0 W 1 PCR31 0 W 0 PCR30 0 W PCR3 is an 8-bit register for controlling whether each of the port 3 pins P37 to P30 functions as an input pin or output pin. Setting a PCR3 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid only when the corresponding pin is designated in PMR3 as a general I/O pin. Upon reset, PCR3 is initialized to H'00. PCR3 is a write-only register, which is always read as all 1s. 3. Port pull-up control register 3 (PUCR3) Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PUCR37 PUCR36 PUCR3 5 PUCR34 PUCR3 3 PUCR3 2 PUCR31 PUCR30 PUCR3 controls whether the MOS pull-up of each of the port 3 pins P37 to P30 is on or off. When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR3 is initialized to H'00. 149 4. Port mode register 3 (PMR3) Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 WDCKS 0 R/W 4 NCS 0 R/W 3 IRQ0 0 R/W 2 RESO 1 R/W 1 UD 0 R/W 0 -- 0 -- PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. Upon reset, PMR3 is initialized to H'04. Bits 7, 6, and 0: Reserved bits These bits are reserved: they are always read as 0 and cannot be modified. Bit 5: Watchdog timer source clock select (WDCKS) This bit selects the watchdog timer source clock. Bit 5 WDCKS 0 1 Description o/8192 selected ow/32 selected (initial value) Bit 4: TMIG noise canceler select (NCS) This bit controls the noise canceler for the input capture input signal (TMIG). Bit 4 NCS 0 1 Description Noise cancellation function not used Noise cancellation function used (initial value) Bit 3: P43/IRQ0 function switch (IRQ0) This bit selects whether P43/IRQ0 is used as P43 or as IRQ0. Bit 3 IRQ0 0 1 Description Functions as P4 3 input Functions as IRQ0 input (initial value) 150 Bit 2: P32/RESO pin function switch (RESO) This bit selects whether pin P32/RESO is used as P32 or as RESO. Bit 2 RESO 0 1 Description Functions as P3 2 I/O pin Functions as RESO output pin (initial value) Bit 1: P31/UD pin function switch (UD) This bit selects whether pin P31/UD is used as P31 or as UD. Bit 1 UD 0 1 Description Functions as P3 1 I/O pin Functions as UD input pin (initial value) 8.4.3 Pin Functions Table 8-9 shows the port 3 pin functions. Table 8-9 Pin P37, P36, P30 Port 3 Pin Functions Pin Functions and Selection Method The pin function depends on bit PCR3n in PCR3. (n=7, 6, 0) PCR3n Pin function 0 P3n input pin 1 P3n output pin P35/TXD31 The pin function depends on bit TE in SCR31, bit SPC31 in SPCR, and bit PCR35 in PCR3. SPC31 TE PCR35 Pin function 0 0 0 P35 input pin 1 P35output pin 1 1 * TXD31 output pin P34/RXD31 The pin function depends on bit RE in SCR31 and bit PCR3 4 in PCR3. RE PCR34 Pin function 0 0 P34 input pin 1 P34 output pin 1 * RXD31 input pin 151 Pin P33/SCK31 Pin Functions and Selection Method The pin function depends on bits CKE1, CKE0, and SMR31 in SCR31 and bit PCR33 in PCR3. CKE1 CKE0 COM31 PCR33 Pin function 0 0 0 0 1 P33 input pin P33 output pin 1 1 * 1 * * * SCK 31 input pin * SCK 31 output pin P32/RESO The pin function depends on bit RESO in PMR3 and bit PCR3 2 in PCR3. RESO PCR32 Pin function 0 0 P32 input pin 1 P32 output pin 1 * RESO output pin P31/UD The pin function depends on bit UD in PMR3 and bit PCR31 in PCR3. UD PCR31 Pin function 0 0 P31 input pin 1 P31 output pin 1 * UD input pin *: Don't care 152 8.4.4 Pin States Table 8-10 shows the port 3 pin states in each operating mode. Table 8-10 Port 3 Pin States Pins P37 P36 P35/TXD31 P34/RXD31 P33/SCK 31 P32/RESO P31/UD P30 Reset Highimpedance Sleep Retains previous state Subsleep Retains previous state Standby Watch Subactive Functional Active Functional HighRetains impedance* previous state Reset output Highimpedance Note: * A high-level signal is output when the MOS pull-up is in the on state. 8.4.5 MOS Input Pull-Up Port 3 has a built-in MOS input pull-up function that can be controlled by software. When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for that pin. The MOS pull-up function is in the off state after a reset. PCR3n PUCR3n MOS input pull-up 0 0 Off 0 1 On 1 * Off (n = 7 to 0) *: Don't care 153 8.5 Port 4* Note: * P4 3/IRQ0, only, is a chip internal input port. 8.5.1 Overview Port 4 is a 3-bit I/O port and 1-bit input internal port, configured as shown in figure 8-4. P43/IRQ0 is an internal function that performs interfacing to the FLEXTM decoder incorporated in the chip. It cannot be connected to an IC outside the chip. P4 3 /IRQ0 Port 4 P4 2 /TXD32 P4 1 /RXD32 P4 0 /SCK32 READY FLEXTM decoder Note: : Connected inside the chip (P43 only). Figure 8-4 Port 4 Pin Configuration 8.5.2 Register Configuration and Description Table 8-11 shows the port 4 register configuration. Table 8-11 Port 4 Registers Name Port data register 4 Port control register 4 Abbrev. PDR4 PCR4 R/W R/W W Initial Value H'F8 H'F8 Address H'FFD7 H'FFE7 154 1. Port data register 4 (PDR4) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 P43 1 R 2 P4 2 0 R/W 1 P4 1 0 R/W 0 P4 0 R/W 0 PDR4 is an 8-bit register that stores data for port 4 pins P42 to P40. If port 4 is read while PCR4 bits are set to 1, the values stored in PDR4 are read, regardless of the actual pin states. If port 4 is read while PCR4 bits are cleared to 0, the pin states are read. Upon reset, PDR4 is initialized to H'F8. 2. Port control register 4 (PCR4) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 PCR42 0 W 1 PCR4 1 0 W 0 PCR4 0 0 W PCR4 is an 8-bit register for controlling whether each of port 4 pins P42 to P40 functions as an input pin or output pin. Setting a PCR4 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. PCR4 and PDR4 settings are valid when the corresponding pins are designated for general-purpose input/output by SCR3-2. Upon reset, PCR4 is initialized to H'F8. PCR4 is a write-only register, which always reads all 1s. 155 8.5.3 Pin Functions Table 8-12 shows the port 4 pin functions. Table 8-12 Port 4 Pin Functions Pin P43/IRQ0 Pin Functions and Selection Method The function depends on bit IRQ0 in PMR3. IRQ0 Function P42/TXD32 0 P43 input 1 IRQ0 input The pin function depends on bit TE in SCR32, bit SPC32 in SPCR, and bit PCR42 in PCR4. SPC32 TE PCR42 Pin function 0 0 0 P42 input pin 1 P42 output pin 1 1 * TXD32 output pin P41/RXD32 The pin function depends on bit RE in SCR32 and bit PCR41 in PCR4. RE PCR41 Pin function 0 0 P41 input pin 1 P41 output pin 1 * RXD32 input pin P40/SCK32 The pin function depends on bits CKE1 and CKE0 in SCR32, bit COM32 in SMR32, and bit PCR4 0 in PCR4. CKE1 CKE0 COM32 PCR40 Pin function 0 0 0 0 P40 input pin 1 P40 output pin 1 1 * 1 * * * SCK 32 input pin *: Don't care * SCK 32 output pin 156 8.5.4 Pin States Table 8-13 shows the port 4 pin states in each operating mode. Table 8-13 Port 4 Pin States Pins P43/IRQ0 Reset High Sleep Retains previous state Subsleep Retains previous state Standby Retains previous state Highimpedance Watch Retains previous state Subactive Functional Active Functional P42/TXD32 P41/RXD32 P40/SCK 32 High impedance 157 8.6 8.6.1 Port 5 Overview Port 5 is an 8-bit I/O port, configured as shown in figure 8-5. P57/WKP7 P56/WKP6 P55/WKP5 Port 5 P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 Figure 8-5 Port 5 Pin Configuration 8.6.2 Register Configuration and Description Table 8-14 shows the port 5 register configuration. Table 8-14 Port 5 Registers Name Port data register 5 Port control register 5 Port pull-up control register 5 Port mode register 5 Abbrev. PDR5 PCR5 PUCR5 PMR5 R/W R/W W R/W R/W Initial Value H'00 H'00 H'00 H'00 Address H'FFD8 H'FFE8 H'FFE2 H'FFCC 158 1. Port data register 5 (PDR5) Bit Initial value Read/Write 7 P5 7 0 R/W 6 P5 6 0 R/W 5 P55 0 R/W 4 P5 4 0 R/W 3 P53 0 R/W 2 P52 0 R/W 1 P51 0 R/W 0 P5 0 0 R/W PDR5 is an 8-bit register that stores data for port 5 pins P57 to P50. If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read. Upon reset, PDR5 is initialized to H'00. 2. Port control register 5 (PCR5) Bit Initial value Read/Write 7 PCR57 0 W 6 PCR56 0 W 5 PCR55 0 W 4 PCR54 0 W 3 PCR53 0 W 2 PCR52 0 W 1 PCR51 0 W 0 PCR50 0 W PCR5 is an 8-bit register for controlling whether each of the port 5 pins P57 to P50 functions as an input pin or output pin. Setting a PCR5 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. PCR5 and PDR5 settings are valid when the corresponding pins are designated for general-purpose input/output by PMR5. Upon reset, PCR5 is initialized to H'00. PCR5 is a write-only register, which is always read as all 1s. 3. Port pull-up control register 5 (PUCR5) Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 PUCR5 controls whether the MOS pull-up of each of port 5 pins P5 7 to P50 is on or off. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR5 is initialized to H'00. 159 4. Port mode register 5 (PMR5) Bit Initial value Read/Write 7 WKP7 0 R/W 6 WKP6 0 R/W 5 WKP5 0 R/W 4 WKP4 0 R/W 3 WKP3 0 R/W 2 WKP2 0 R/W 1 WKP1 0 R/W 0 WKP0 0 R/W PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins. Upon reset, PMR5 is initialized to H'00. Bit n: P5n/WKPn pin function switch (WKPn) These bits select whether the pin is used as P5n or WKPn. Bit n WKPn 0 1 Description Functions as P5 n I/O pin Functions as WKP n input pin (n = 7 to 0) (initial value) 8.6.3 Pin Functions Table 8-15 shows the port 5 pin functions. Table 8-15 Port 5 Pin Functions Pin P57/WKP 7 to P50/WKP 0 WKP n PCR5n Pin function 0 0 1 1 * WKP n input pin *: Don't care Pin Functions and Selection Method The pin function depends on bit WKP n in PMR5 and bit PCR5n in PCR5. (n = 7 to 0) P5n input pin P5n output pin 160 8.6.4 Pin States Table 8-16 shows the port 5 pin states in each operating mode. Table 8-16 Port 5 Pin States Pins P57/WKP7 to P50/ WKP0 Reset Highimpedance Sleep Retains previous state Subsleep Retains previous state Standby Watch Subactive Functional Active Functional HighRetains impedance* previous state Note: * A high-level signal is output when the MOS pull-up is in the on state. 8.6.5 MOS Input Pull-Up Port 5 has a built-in MOS input pull-up function that can be controlled by software. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for that pin. The MOS pull-up function is in the off state after a reset. PCR5n PUCR5n MOS input pull-up 0 0 Off 0 1 On 1 * Off (n = 7 to 0) *: Don't care 161 8.7 8.7.1 Port 6 Overview Port 6 is an 8-bit I/O port. The port 6 pin configuration is shown in figure 8-6. P67 P66 P65 Port 6 P64 P63 P62 P61 P60 Figure 8-6 Port 6 Pin Configuration 8.7.2 Register Configuration and Description Table 8-17 shows the port 6 register configuration. Table 8-17 Port 6 Registers Name Port data register 6 Port control register 6 Port pull-up control register 6 Abbrev. PDR6 PCR6 PUCR6 R/W R/W W R/W Initial Value H'00 H'00 H'00 Address H'FFD9 H'FFE9 H'FFE3 162 1. Port data register 6 (PDR6) Bit Initial value Read/Write 7 P6 7 0 R/W 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W 3 P6 3 0 R/W 2 P62 0 R/W 1 P61 0 R/W 0 P6 0 0 R/W PDR6 is an 8-bit register that stores data for port 6 pins P67 to P60. If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the actual pin states. If port 6 is read while PCR6 bits are cleared to 0, the pin states are read. Upon reset, PDR6 is initialized to H'00. 2. Port control register 6 (PCR6) Bit Initial value Read/Write 7 PCR67 0 W 6 PCR66 0 W 5 PCR65 0 W 4 PCR64 0 W 3 PCR63 0 W 2 PCR62 0 W 1 PCR61 0 W 0 PCR60 0 W PCR6 is an 8-bit register for controlling whether each of the port 6 pins P67 to P60 functions as an input pin or output pin. Setting a PCR6 bit to 1 makes the corresponding pin (P6 7 to P60) an output pin, while clearing the bit to 0 makes the pin an input pin. Upon reset, PCR6 is initialized to H'00. PCR6 is a write-only register, which always reads all 1s. 3. Port pull-up control register 6 (PUCR6) Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PUCR67 PUCR66 PUCR6 5 PUCR64 PUCR6 3 PUCR6 2 PUCR61 PUCR60 PUCR6 controls whether the MOS pull-up of each of the port 6 pins P67 to P60 is on or off. When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR6 is initialized to H'00. 163 8.7.3 Pin Functions Table 8-18 shows the port 6 pin functions. Table 8-18 Port 6 Pin Functions Pin P67 to P6 0 Pin Functions and Selection Method The pin function depends on bit PCR6n in PCR6. (n = 7 to 0) PCR6n Pin function 0 P6n input pin 1 P6n output pin 8.7.4 Pin States Table 8-19 shows the port 6 pin states in each operating mode. Table 8-19 Port 6 Pin States Pins P67 to P60 Reset Highimpedance Sleep Retains previous state Subsleep Retains previous state Standby Watch Subactive Functional Active Functional HighRetains impedance* previous state Note: * A high-level signal is output when the MOS pull-up is in the on state. 8.7.5 MOS Input Pull-Up Port 6 has a built-in MOS pull-up function that can be controlled by software. When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for that pin. The MOS pull-up function is in the off state after a reset. PCR6n PUCR6n MOS input pull-up 0 0 Off 0 1 On 1 * Off (n = 7 to 0) *: Don't care 164 8.8 8.8.1 Port 7 Overview Port 7 is an 8-bit I/O port, configured as shown in figure 8-7. P77 P76 P75 Port 7 P74 P73 P72 P71 P70 Figure 8-7 Port 7 Pin Configuration 8.8.2 Register Configuration and Description Table 8-20 shows the port 7 register configuration. Table 8-20 Port 7 Registers Name Port data register 7 Port control register 7 Abbrev. PDR7 PCR7 R/W R/W W Initial Value H'00 H'00 Address H'FFDA H'FFEA 165 1. Port data register 7 (PDR7) Bit Initial value Read/Write 7 P7 7 0 R/W 6 P7 6 0 R/W 5 P75 0 R/W 4 P7 4 0 R/W 3 P73 0 R/W 2 P72 0 R/W 1 P71 0 R/W 0 P70 0 R/W PDR7 is an 8-bit register that stores data for port 7 pins P77 to P70. If port 7 is read while PCR7 bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is read while PCR7 bits are cleared to 0, the pin states are read. Upon reset, PDR7 is initialized to H'00. 2. Port control register 7 (PCR7) Bit Initial value Read/Write 7 PCR77 0 W 6 PCR76 0 W 5 PCR75 0 W 4 PCR74 0 W 3 PCR73 0 W 2 PCR72 0 W 1 PCR71 0 W 0 PCR70 0 W PCR7 is an 8-bit register for controlling whether each of the port 7 pins P77 to P70 functions as an input pin or output pin. Setting a PCR7 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. Upon reset, PCR7 is initialized to H'00. PCR7 is a write-only register, which always reads as all 1s. 166 8.8.3 Pin Functions Table 8-21 shows the port 7 pin functions. Table 8-21 Port 7 Pin Functions Pin P77 to P7 0 Pin Functions and Selection Method The pin function depends on bit PCR7n in PCR7. (n = 7 to 0) PCR7n Pin function 0 P7n input pin 1 P7n output pin 8.8.4 Pin States Table 8-22 shows the port 7 pin states in each operating mode. Table 8-22 Port 7 Pin States Pins P77 to P70 Reset Highimpedance Sleep Retains previous state Subsleep Retains previous state Standby Highimpedance Watch Retains previous state Subactive Functional Active Functional 167 8.9 8.9.1 Port 8 Overview Port 8 is an 8-bit I/O port configured as shown in figure 8-8. P87 P86 P85 Port 8 P84 P83 P82 P81 P80 Figure 8-8 Port 8 Pin Configuration 8.9.2 Register Configuration and Description Table 8-23 shows the port 8 register configuration. Table 8-23 Port 8 Registers Name Port data register 8 Port control register 8 Abbrev. PDR8 PCR8 R/W R/W W Initial Value H'00 H'00 Address H'FFDB H'FFEB 1. Port data register 8 (PDR8) Bit Initial value Read/Write 7 P8 7 0 R/W 6 P8 6 0 R/W 5 P85 0 R/W 4 P8 4 0 R/W 3 P83 0 R/W 2 P82 0 R/W 1 P81 0 R/W 0 P8 0 0 R/W PDR8 is an 8-bit register that stores data for port 8 pins P87 to P80. If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read. Upon reset, PDR8 is initialized to H'00. 168 2. Port control register 8 (PCR8) Bit Initial value Read/Write 7 PCR87 0 W 6 PCR86 0 W 5 PCR85 0 W 4 PCR84 0 W 3 PCR83 0 W 2 PCR82 0 W 1 PCR81 0 W 0 PCR80 0 W PCR8 is an 8-bit register for controlling whether each of the port 8 pins P87 to P80 functions as an input or output pin. Setting a PCR8 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. Upon reset, PCR8 is initialized to H'00. PCR8 is a write-only register, which is always read as all 1s. 8.9.3 Pin Functions Table 8-24 shows the port 8 pin functions. Table 8-24 Port 8 Pin Functions Pin P87 to P8 0 Pin Functions and Selection Method The pin function depends on bit PCR8n in PCR8. (n = 7 to 0) PCR8n Pin function 0 P8n input pin 1 P8n output pin 8.9.4 Pin States Table 8-25 shows the port 8 pin states in each operating mode. Table 8-25 Port 8 Pin States Pins P87 to P80 Reset Highimpedance Sleep Retains previous state Subsleep Retains previous state Standby Highimpedance Watch Retains previous state Subactive Functional Active Functional 169 8.10 8.10.1 Port 9 Overview Port 9 is a 4-bit I/O port. Figure 8-9 shows its pin configuration. P93 Port 9 P92 P91 P90 Figure 8-9 Port 9 Pin Configuration 8.10.2 Register Configuration and Description Table 8-26 shows the port 9 register configuration. Table 8-26 Port 9 Registers Name Port data register 9 Port control register 9 Abbrev. PDR9 PCR9 R/W R/W R Initial Value H'00 H'F0 Address H'FFDC H'FFEC 170 1. Port data register 9 (PDR9) Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 P93 0 R/W 2 P92 0 R/W 1 P91 0 R/W 0 P90 0 R/W PDR9 is an 8-bit register that stores data for port 9 pins P93 to P90. If port 9 is read while PCR9 bits are set to 1, the values stored in PDR9 are read, regardless of the actual pin states. If port 9 is read while PCR9 bits are cleared to 0, the pin states are read. Upon reset, PDR9 is initialized to H'F0. 2. Port control register 9 (PCR9) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PCR93 0 W 2 PCR92 0 W 1 PCR91 0 W 0 PCR90 0 W PCR9 is an 8-bit register for controlling whether each of the port 9 pins P93 to P90 functions as an input pin or output pin. Setting a PCR9 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. Upon reset, PCR9 is initialized to H'F0. PCR9 is a write-only register, which is always read as all 1s. 171 8.10.3 Pin Functions Table 8-27 shows the port 9 pin functions. Table 8-27 Port 9 Pin Functions Pin P93 to P9 0 Pin Functions and Selection Method The pin function depends on bit PCR9n in PCR9. (n = 3 to 0) PCR9n Pin function 0 P9n input pin 1 P9n output pin 8.10.4 Pin States Table 8-28 shows the port 9 pin states in each operating mode. Table 8-28 Port 9 Pin States Pins P93 to P90 Reset Highimpedance Sleep Retains previous state Subsleep Retains previous state Standby Highimpedance Watch Retains previous state Subactive Functional Active Functional 172 8.11 8.11.1 Port A Overview Port A is a 4-bit I/O port, configured as shown in figure 8-10. PA3 Port A PA2 PA1 PA0 Figure 8-10 Port A Pin Configuration 8.11.2 Register Configuration and Description Table 8-29 shows the port A register configuration. Table 8-29 Port A Registers Name Port data register A Port control register A Abbrev. PDRA PCRA R/W R/W W Initial Value H'F0 H'F0 Address H'FFDD H'FFED 1. Port data register A (PDRA) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PA 3 0 R/W 2 PA 2 0 R/W 1 PA 1 0 R/W 0 PA 0 0 R/W PDRA is an 8-bit register that stores data for port A pins PA3 to PA 0. If port A is read while PCRA bits are set to 1, the values stored in PDRA are read, regardless of the actual pin states. If port A is read while PCRA bits are cleared to 0, the pin states are read. Upon reset, PDRA is initialized to H'F0. 173 2. Port control register A (PCRA) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PCRA 3 0 R/W 2 PCRA 2 0 R/W 1 PCRA 1 0 R/W 0 PCRA 0 0 R/W PCRA controls whether each of port A pins PA3 to PA 0 functions as an input pin or output pin. Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. Upon reset, PCRA is initialized to H'F0. PCRA is a write-only register, which always reads all 1s. 8.11.3 Pin Functions Table 8-30 shows the port A pin functions. Table 8-30 Port A Pin Functions Pin PA3 to PA 0 Pin Functions and Selection Method The pin function depends on bit PCRAn in PCRA. (n = 3 to 0) PCRAn Pin function 0 PAn input pin 1 PAn output pin 8.11.4 Pin States Table 8-31 shows the port A pin states in each operating mode. Table 8-31 Port A Pin States Pins PA 3 to PA0 Reset Highimpedance Sleep Retains previous state Subsleep Retains previous state Standby Highimpedance Watch Retains previous state Subactive Functional Active Functional 174 8.12 8.12.1 Port B Overview Port B is an 8-bit input-only port, configured as shown in figure 8-11. PB7/AN7 PB6/AN6 PB5/AN5 Port B PB4/AN4 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 Figure 8-11 Port B Pin Configuration 8.12.2 Register Configuration and Description Table 8-32 shows the port B register configuration. Table 8-32 Port B Register Name Port data register B Abbrev. PDRB R/W R Address H'FFDE Port Data Register B (PDRB) Bit 7 PB7 Read/Write R 6 PB6 R 5 PB5 R 4 PB4 R 3 PB3 R 2 PB2 R 1 PB1 R 0 PB 0 R Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input voltage. 175 8.13 8.13.1 Input/Output Data Inversion Function Overview With input pins RXD31, and RXD32, and output pins TXD31 and TXD32, the data can be handled in inverted form. SCINV0 SCINV2 P34/RXD31 P41/RXD32 SCINV1 SCINV3 P35/TXD31 P42/TXD32 TXD31 TXD32 RXD31 RXD32 Figure 8.12 Input/Output Data Inversion Function 8.13.2 Register Configuration and Descriptions Table 8.33 shows the registers used by the input/output data inversion function. Table 8.33 Register Configuration Name Serial port control register Abbreviation SPCR R/W R/W Initial Value H'C0 Address H'FF91 Serial Port Control Register (SPCR) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 SPC32 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W SPC31 SCINV3 SCINV2 SCINV1 SCINV0 SPCR is an 8-bit readable/writable register that performs RXD31, RXD32, TXD31, and TXD32 pin input/output data inversion switching. SPCR is initialized to H'C0 by a reset. 176 Bits 7 and 6: Reserved bits Bits 7 and 6 are reserved; they are always read as 1 and cannot be modified. Bit 5: P42/TXD32 pin function switch (SPC32) This bit selects whether pin P42/TXD32 is used as P42 or as TXD32. Bit 5 SPC32 0 1 Note: * Description Functions as P4 2 I/O pin Functions as TXD 32 output pin* Set the TE bit in SCR3 after setting this bit to 1. (initial value) Bit 4: P35/TXD 31 pin function switch (SPC31) This bit selects whether pin P35/TXD31 is used as P35 or as TXD31. Bit 4 SPC31 0 1 Note: * Description Functions as P3 5 I/O pin Functions as TXD 31 output pin* Set the TE bit in SCR3 after setting this bit to 1. (initial value) Bit 3: TXD32 pin output data inversion switch Bit 3 specifies whether or not TXD32 pin output data is to be inverted. Bit 3 SCINV3 0 1 Description TXD32 output data is not inverted TXD32 output data is inverted (initial value) Bit 2: RXD 32 pin input data inversion switch Bit 2 specifies whether or not RXD 32 pin input data is to be inverted. Bit 2 SCINV2 0 1 Description RXD32 input data is not inverted RXD32 input data is inverted (initial value) 177 Bit 1: TXD31 pin output data inversion switch Bit 1 specifies whether or not TXD31 pin output data is to be inverted. Bit 1 SCINV1 0 1 Description TXD31 output data is not inverted TXD31 output data is inverted (initial value) Bit 0: RXD 31 pin input data inversion switch Bit 0 specifies whether or not RXD 31 pin input data is to be inverted. Bit 0 SCINV0 0 1 Description RXD31 input data is not inverted RXD31 input data is inverted (initial value) 8.13.3 Note on Modification of Serial Port Control Register When a serial port control register is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input or output. When modifying a serial port control register, do so in a state in which data changes are invalidated 8.14 8.14.1 Application Note The Management of the Un-Use Terminal If an I/O pin not used by the user system is floating, pull it up or down. * If an unused pin is an input pin, handle it in one of the following ways: Pull it up to V CC with an on-chip pull-up MOS. Pull it up to V CC with an external resister of approximately 100 k. Pull it down to VSS with an external resister of approximately 100 k. * If an unused pin is an output pin, handle it in one of the following ways: Set the output of the unused pin to high and pull it up to VCC with an on-chip pull-up MOS. Set the output of the unused pin to high and pull it up to VCC with an external resister of approximately 100 k. Set the output of the unused pin to low and pull it down to VSS with an external resister of approximately 100 k. 178 Section 9 Timers 9.1 Overview The H8/3937 Series and H8/3937R Series provide five timers: timers A, C, F, G, and a watchdog timer. The functions of these timers are outlined in table 9-1. Table 9-1 Name Timer A Timer Functions Functions * 8-bit interval timer * Interval function * Time base * Clock output Internal Clock o/8 to o/8192 (8 choices) oW/128 (choice of 4 overflow periods) o/4 to o/32 o W , oW/4 -- to o W /32 (9 choices) TMOW -- Up- count/ down-count controllable by software or hardware Event Waveform Input Pin Output Pin Remarks -- -- Timer C o/4 to o/8192, oW/4 TMIC * 8-bit timer (7 choices) * Interval function * Event counting function * Up-count/down-count selectable o/4 to o/32, oW/4 * 16-bit timer * Event counting function (4 choices) * Also usable as two independent 8-bit timers * Output compare output function * 8-bit timer * Input capture function * Interval function o/2 to o/64, oW/4 (4 choices) TMIF Timer F TMOFL TMOFH Timer G TMIG -- Counter clearing option Built-in capture input signal noise canceler Watchdog timer * Reset signal generated o/8192 ow/32 when 8-bit counter overflows -- -- 179 9.2 9.2.1 Timer A Overview Timer A is an 8-bit timer with interval timing and time-base functions. A clock signal divided from 76.8 kHz (if a 76.8 kHz crystal oscillator is connected), from 160 kHz (if a 160 kHz crystal oscillator is connected), or from the system clock, can be output at the TMOW pin. 1. Features Features of timer A are given below. * Choice of eight internal clock sources (o/8192, o/4096, o/2048, o/512, o/256, o/128, o/32, o/8). * Choice of four overflow periods (o w/32768, ow/16384, ow /8192, ow/1024) when timer A is used as a time base. * An interrupt is requested when the counter overflows. * Any of nine clock signals can be output at the TMOW pin: ow divided by 32, 16, 8, or 4 and the system clock divided by 32, 16, 8, or 4. * Use of module standby mode enables this module to be placed in standby mode independently when not used. 180 2. Block diagram Figure 9-1 shows a block diagram of timer A. oW CWORS 1/4 oW/4 PSW TMA oW/32 oW/16 oW/8 oW/4 TMOW o/32 o/16 o/8 o/4 o oW /128 TCA /128* o/8192, o/4096, o/2048, o/512, o/256, o/128, o/32, o/8 /256* /64* /8* PSS IRRTA Notation: TMA: TCA: IRRTA: PSW: PSS: CWOSR: Timer mode register A Timer counter A Timer A overflow interrupt request flag Prescaler W Prescaler S Subclock output select register Note: * Can be selected only when the prescaler W output (oW/128) is used as the TCA input clock. Figure 9-1 Block Diagram of Timer A 3. Pin configuration Table 9-2 shows the timer A pin configuration. Table 9-2 Name Clock output Pin Configuration Abbrev. TMOW I/O Output Function Output of waveform generated by timer A output circuit Internal data bus 181 4. Register configuration Table 9-3 shows the register configuration of timer A. Table 9-3 Name Timer mode register A Timer counter A Clock stop register 1 Subclock output select register Timer A Registers Abbrev. TMA TCA CKSTPR1 CWOSR R/W R/W R R/W R/W Initial Value H'10 H'00 H'FF H'FE Address H'FFB0 H'FFB1 H'FFFA H'FF92 9.2.2 Register Descriptions 1. Timer mode register A (TMA) Bit Initial value Read/Write 7 TMA7 0 R/W 6 TMA6 0 R/W 5 TMA5 0 R/W 4 -- 1 -- 3 TMA3 0 R/W 2 TMA2 0 R/W 1 TMA1 0 R/W 0 TMA0 0 R/W TMA is an 8-bit read/write register for selecting the prescaler, input clock, and output clock. Upon reset, TMA is initialized to H'10. 182 Bits 7 to 5: Clock output select (TMA7 to TMA5) Bits 7 to 5 choose which of eight clock signals is output at the TMOW pin. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A ow signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode. ow is output in all modes except the reset state. CWOSR CWOS 0 TMA Bit 7 TMA7 0 Bit 6 TMA6 0 Bit 5 TMA5 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Clock Output o/32 o/16 o/8 o/4 oW/32 oW/16 oW/8 oW/4 oW *: Don't care (initial value) Bit 4: Reserved bit Bit 4 is reserved; it is always read as 1, and cannot be modified. 183 Bits 3 to 0: Internal clock select (TMA3 to TMA0) Bits 3 to 0 select the clock input to TCA. The selection is made as follows. Description Bit 3 TMA3 0 Bit 2 TMA2 0 Bit 1 TMA1 0 Bit 0 TMA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Prescaler and Divider Ratio or Overflow Period PSS, o/8192 PSS, o/4096 PSS, o/2048 PSS, o/512 PSS, o/256 PSS, o/128 PSS, o/32 PSS, o/8 PSW, ow /32768 PSW, ow /16384 PSW, ow /8192 PSW, ow /1024 PSW and TCA are reset Time base (overflow period) Function (initial value) Interval timer 184 2. Timer counter A (TCA) Bit Initial value Read/Write 7 TCA7 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R 2 TCA2 0 R 1 TCA1 0 R 0 TCA0 0 R TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A (TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1. TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11. Upon reset, TCA is initialized to H'00. 3. Clock stop register 1 (CKSTPR1) Bit 7 6 5 4 3 2 1 0 S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value Read/Write 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer A is described here. For details of the other bits, see the sections on the relevant modules. Bit 0: Timer A module standby mode control (TACKSTP) Bit 0 controls setting and clearing of module standby mode for timer A. TACKSTP 0 1 Description Timer A is set to module standby mode Timer A module standby mode is cleared (initial value) 185 4. Subclock Output Select Register (CWOSR) Bit: Initial value: Read/Write: 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 CWOS 0 R/W 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- CWOSR is an 8-bit read/write register that selects the clock to be output from the TMOW pin. CWOSR is initialized to H'FE by a reset. Bits 7 to 1: Reserved bits Bits 7 to 1 are reserved; they are always read as 1 and cannot be modified. Bit 0: TMOW pin clock select (CWOS) Bit 0 selects the clock to be output from the TMOW pin. Bit 0 CWOS 0 1 Description Clock output from timer A is output (see TMA) oW is output (initial value) 9.2.3 Timer Operation 1. Interval timer operation When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in TMA; any of eight internal clock signals output by prescaler S can be selected. After the count value in TCA reaches H'FF, the next clock signal input causes timer A to overflow, setting bit IRRTA to 1 in interrupt request register 1 (IRR1). If IENTA = 1 in interrupt enable register 1 (IENR1), a CPU interrupt is requested.* At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. Note: * For details on interrupts, see 3.3, Interrupts. 186 2. Time base operation When bit TMA3 in TMA is set to 1, timer A functions as a time base by counting clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available. In time base operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA and prescaler W to their initial values of H'00. 3. Clock output Setting bit TMOW in port mode register 1 (PMR1) to 1 causes a clock signal to be output at pin TMOW. Nine different clock output signals can be selected by means of bits TMA7 to TMA5 in TMA and bit CWOS in CWOSR. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A o w signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, watch mode, subactive mode, and subsleep mode. The ow clock is output in all modes except the reset state. 9.2.4 Timer A Operation States Table 9-4 summarizes the timer A operation states. Table 9-4 Timer A Operation States Subactive Halted Subsleep Halted Module Standby Halted Halted Operation Mode TCA Interval Time base TMA Reset Active Sleep Watch Standby Halted Reset Functions Functions Halted Reset Functions Functions Functions Functions Functions Halted Reset Functions Retained Retained Functions Retained Retained Retained Note: When the time base function is selected as the internal clock of TCA in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/o (s) in the count cycle. 9.2.5 Application Note When bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) is cleared to 0, bit 3 (TMA3) of the timer mode register A (TMA) cannot be rewritten. Set bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) to 1 before rewriting bit 3 (TMA3) of the timer mode register A (TMA). 187 9.3 9.3.1 Timer C Overview Timer C is an 8-bit timer that increments each time a clock pulse is input. This timer has two operation modes, interval and auto reload. 1. Features Features of timer C are given below. * Choice of seven internal clock sources (o/8192, o/2048, o/512, o/64, o/16, o/4, o W /4) or an external clock (can be used to count external events). * An interrupt is requested when the counter overflows. * Up/down-counter switching is possible by hardware or software. * Subactive mode and subsleep mode operation is possible when oW/4 is selected as the internal clock, or when an external clock is selected. * Use of module standby mode enables this module to be placed in standby mode independently when not used. 188 2. Block diagram Figure 9-2 shows a block diagram of timer C. TMC UD TCC o TMIC oW/4 TLC PSS IRRTC Notation: TMC TCC TLC PSS : Timer mode register C : Timer counter C : Timer load register C : Prescaler S IRRTC : Timer C overflow interrupt request flag Figure 9-2 Block Diagram of Timer C 3. Pin configuration Table 9-5 shows the timer C pin configuration. Table 9-5 Name Timer C event input Timer C up/down-count selection Pin Configuration Abbrev. TMIC UD I/O Input Input Function Input pin for event input to TCC Timer C up/down select 189 Internal data bus 4. Register configuration Table 9-6 shows the register configuration of timer C. Table 9-6 Name Timer mode register C Timer counter C Timer load register C Clock stop register 1 Timer C Registers Abbrev. TMC TCC TLC CKSTPR1 R/W R/W R W R/W Initial Value H'18 H'00 H'00 H'FF Address H'FFB4 H'FFB5 H'FFB5 H'FFFA 9.3.2 Register Descriptions 1. Timer mode register C (TMC) Bit Initial value Read/Write 7 TMC7 0 R/W 6 TMC6 0 R/W 5 TMC5 0 R/W 4 -- 1 -- 3 -- 1 -- 2 TMC2 0 R/W 1 TMC1 0 R/W 0 TMC0 0 R/W TMC is an 8-bit read/write register for selecting the auto-reload function and input clock, and performing up/down-counter control. Upon reset, TMC is initialized to H'18. Bit 7: Auto-reload function select (TMC7) Bit 7 selects whether timer C is used as an interval timer or auto-reload timer. Bit 7 TMC7 0 1 Description Interval timer function selected Auto-reload function selected (initial value) 190 Bits 6 and 5: Counter up/down control (TMC6, TMC5) Selects whether TCC up/down control is performed by hardware using UD pin input, or whether TCC functions as an up-counter or a down-counter. Bit 6 TMC6 0 0 1 Bit 5 TMC5 0 1 * Description TCC is an up-counter TCC is a down-counter Hardware control by UD pin input UD pin input high: Down-counter UD pin input low: Up-counter *: Don't care (initial value) Bits 4 and 3: Reserved bits Bits 4 and 3 are reserved; they are always read as 1 and cannot be modified. Bits 2 to 0: Clock select (TMC2 to TMC0) Bits 2 to 0 select the clock input to TCC. For external event counting, either the rising or falling edge can be selected. Bit 2 TMC2 0 0 0 0 1 1 1 1 Bit 1 TMC1 0 0 1 1 0 0 1 1 Bit 0 TMC0 0 1 0 1 0 1 0 1 Description Internal clock: o/8192 Internal clock: o/2048 Internal clock: o/512 Internal clock: o/64 Internal clock: o/16 Internal clock: o/4 Internal clock: o W /4 External event (TMIC): rising or falling edge* (initial value) Note: * The edge of the external event signal is selected by bit IEG1 in the IRQ edge select register (IEGR). See 1. IRQ edge select register (IEGR) in 3.3.2 for details. IRQ2 must be set to 1 in port mode register 1 (PMR1) before setting 111 in bits TMC2 to TMC0. 191 2. Timer counter C (TCC) Bit Initial value Read/Write 7 TCC7 0 R 6 TCC6 0 R 5 TCC5 0 R 4 TCC4 0 R 3 TCC3 0 R 2 TCC2 0 R 1 TCC1 0 R 0 TCC0 0 R TCC is an 8-bit read-only up-counter, which is incremented by internal clock or external event input. The clock source for input to this counter is selected by bits TMC2 to TMC0 in timer mode register C (TMC). TCC values can be read by the CPU at any time. When TCC overflows from H'FF to H'00 or to the value set in TLC, or underflows from H'00 to H'FF or to the value set in TLC, the IRRTC bit in IRR2 is set to 1. TCC is allocated to the same address as TLC. Upon reset, TCC is initialized to H'00. 3. Timer load register C (TLC) Bit Initial value Read/Write 7 TLC7 0 W 6 TLC6 0 W 5 TLC5 0 W 4 TLC4 0 W 3 TLC3 0 W 2 TLC2 0 W 1 TLC1 0 W 0 TLC0 0 W TLC is an 8-bit write-only register for setting the reload value of timer counter C (TCC). When a reload value is set in TLC, the same value is loaded into timer counter C as well, and TCC starts counting up from that value. When TCC overflows or underflows during operation in autoreload mode, the TLC value is loaded into TCC. Accordingly, overflow/underflow periods can be set within the range of 1 to 256 input clocks. The same address is allocated to TLC as to TCC. Upon reset, TLC is initialized to H'00. 4. Clock stop register 1 (CKSTPR1) Bit 7 6 5 4 3 2 1 0 S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value Read/Write 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 192 CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer C is described here. For details of the other bits, see the sections on the relevant modules. Bit 1: Timer C module standby mode control (TCCKSTP) Bit 1 controls setting and clearing of module standby mode for timer C. TCCKSTP 0 1 Description Timer C is set to module standby mode Timer C module standby mode is cleared (initial value) 9.3.3 Timer Operation 1. Interval timer operation When bit TMC7 in timer mode register C (TMC) is cleared to 0, timer C functions as an 8-bit interval timer. Upon reset, TCC is initialized to H'00 and TMC to H'18, so TCC continues up-counting as an interval up-counter without halting immediately after a reset. The timer C operating clock is selected from seven internal clock signals output by prescalers S and W, or an external clock input at pin TMIC. The selection is made by bits TMC2 to TMC0 in TMC. TCC up/down-count control can be performed either by software or hardware. The selection is made by bits TMC6 and TMC5 in TMC. After the count value in TCC reaches H'FF (H'00), the next clock input causes timer C to overflow (underflow), setting bit IRRTC to 1 in IRR2. If IENTC = 1 in interrupt enable register 2 (IENR2), a CPU interrupt is requested. At overflow (underflow), TCC returns to H'00 (H'FF) and starts counting up (down) again. During interval timer operation (TMC7 = 0), when a value is set in timer load register C (TLC), the same value is set in TCC. Note: * For details on interrupts, see 3.3, Interrupts. 193 2. Auto-reload timer operation Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a reload value is set in TLC, the same value is loaded into TCC, becoming the value from which TCC starts its count. After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to overflow/underflow. The TLC value is then loaded into TCC, and the count continues from that value. The overflow/underflow period can be set within a range from 1 to 256 input clocks, depending on the TLC value. The clock sources, up/down control, and interrupts in auto-reload mode are the same as in interval mode. In auto-reload mode (TMC7 = 1), when a new value is set in TLC, the TLC value is also set in TCC. 3. Event counter operation Timer C can operate as an event counter, counting rising or falling edges of an external event signal input at pin TMIC. External event counting is selected by setting bits TMC2 to TMC0 in timer mode register C to all 1s (111). When timer C is used to count external event input, , bit IRQ2 in PMR1 should be set to 1 and bit IEN2 in IENR1 cleared to 0 to disable interrupt IRQ2 requests. 4. TCC up/down control by hardware With timer C, TCC up/down control can be performed by UD pin input. When bit TMC6 is set to 1 in TMC, TCC functions as an up-counter when UD pin input is high, and as a down-counter when low. When using UD pin input, set bit UD to 1 in PMR3. 194 9.3.4 Timer C Operation States Table 9-7 summarizes the timer C operation states. Table 9-7 Timer C Operation States Subactive Subsleep Module Standby Halted Halted Retained Operation Mode TCC Interval Auto reload TMC Reset Reset Reset Reset Active Sleep Watch Standby Functions Functions Halted Functions Functions Halted Functions Retained Retained Functions/ Functions/ Halted Halted* Halted* Functions/ Functions/ Halted Halted* Halted* Functions Retained Retained Note: * When ow/4 is selected as the TCC internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. This results in a maximum count cycle error of 1/o (s). When the counter is operated in subactive mode or subsleep mode, either select ow/4 as the internal clock or select an external clock. The counter will not operate on any other internal clock. If ow/4 is selected as the internal clock for the counter when ow/8 has been selected as subclock oSUB, the lower 2 bits of the counter operate on the same cycle, and the operation of the least significant bit is unrelated to the operation of the counter. 195 9.4 9.4.1 Timer F Overview Timer F is a 16-bit timer with a built-in output compare function. As well as counting external events, timer F also provides for counter resetting, interrupt request generation, toggle output, etc., using compare match signals. Timer F can also be used as two independent 8-bit timers (timer FH and timer FL). 1. Features Features of timer F are given below. * Choice of four internal clock sources (o/32, o/16, o/4, ow/4) or an external clock (can be used as an external event counter) * TMOFH pin toggle output provided using a single compare match signal (toggle output initial value can be set) * Counter resetting by a compare match signal * Two interrupt sources: one compare match, one overflow * Can operate as two independent 8-bit timers (timer FH and timer FL) (in 8-bit mode). Timer FH 8-Bit Timer* Internal clock Event input Toggle output Choice of 4 (o/32, o/16, o/4, ow/4) -- One compare match signal, output to TMOFH pin (initial value settable) TMIF pin One compare match signal, output to TMOFL pin (initial value settable) Timer FL 8-Bit Timer/Event Counter Counter reset Interrupt sources Note: * Counter can be reset by compare match signal One compare match One overflow When timer F operates as a 16-bit timer, it operates on the timer FL overflow signal. * Operation in watch mode, subactive mode, and subsleep mode When ow/4 is selected as the internal clock, timer F can operate in watch mode, subactive mode, and subsleep mode. * Use of module standby mode enables this module to be placed in standby mode independently when not used. 196 2. Block diagram Figure 9-3 shows a block diagram of timer F. o PSS IRRTFL TCRF ow/4 TMIF TMOFL Toggle circuit TCFL Comparator OCRFL Internal data bus TCFH TMOFH Toggle circuit Comparator OCRFH TCSRF Legend TCRF : Timer control register F TCSRF : Timer control status register F TCFH : 8-bit timer counter FH TCFL : 8-bit timer counter FL OCRFH : Output compare register FH OCRFL : Output compare register FL IRRTFH : Timer FH interrupt request flag IRRTFL : Timer FL interrupt request flag PSS : Prescaler S Match IRRTFH Figure 9-3 Block Diagram of Timer F 197 3. Pin configuration Table 9-8 shows the timer F pin configuration. Table 9-8 Name Timer F event input Timer FH output Timer FL output Pin Configuration Abbrev. TMIF TMOFH TMOFL I/O Input Output Output Function Event input pin for input to TCFL Timer FH toggle output pin Timer FL toggle output pin 4. Register configuration Table 9-9 shows the register configuration of timer F. Table 9-9 Name Timer control register F Timer control/status register F 8-bit timer counter FH 8-bit timer counter FL Output compare register FH Output compare register FL Clock stop register 1 Timer F Registers Abbrev. TCRF TCSRF TCFH TCFL OCRFH OCRFL CKSTPR1 R/W W R/W R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'00 H'00 H'FF H'FF H'FF Address H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFFA 198 9.4.2 Register Descriptions 1. 16-bit timer counter (TCF) 8-bit timer counter (TCFH) 8-bit timer counter (TCFL) TCF Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: Read/Write: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCFH TCFL TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters TCFH and TCFL. In addition to the use of TCF as a 16-bit counter with TCFH as the upper 8 bits and TCFL as the lower 8 bits, TCFH and TCFL can also be used as independent 8-bit counters. TCFH and TCFL can be read and written by the CPU, but when they are used in 16-bit mode, data transfer to and from the CPU is performed via a temporary register (TEMP). For details of TEMP, see 9.4.3, CPU Interface. TCFH and TCFL are each initialized to H'00 upon reset. a. 16-bit mode (TCF) When CKSH2 is cleared to 0 in TCRF, TCF operates as a 16-bit counter. The TCF input clock is selected by bits CKSL2 to CKSL0 in TCRF. TCF can be cleared in the event of a compare match by means of CCLRH in TCSRF. When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in TCSRF is 1 at this time, IRRTFH is set to 1 in IRR2, and if IENTFH in IENR2 is 1, an interrupt request is sent to the CPU. b. 8-bit mode (TCFL/TCFH) When CKSH2 is set to 1 in TCRF, TCFH and TCFL operate as two independent 8-bit counters. The TCFH (TCFL) input clock is selected by bits CKSH2 to CKSH0 (CKSL2 to CKSL0) in TCRF. TCFH (TCFL) can be cleared in the event of a compare match by means of CCLRH (CCLRL) in TCSRF. When TCFH (TCFL) overflows from H'FF to H'00, OVFH (OVFL) is set to 1 in TCSRF. If OVIEH (OVIEL) in TCSRF is 1 at this time, IRRTFH (IRRTFL) is set to 1 in IRR2, and if IENTFH (IENTFL) in IENR2 is 1, an interrupt request is sent to the CPU. 199 2. 16-bit output compare register (OCRF) 8-bit output compare register (OCRFH) 8-bit output compare register (OCRFL) OCRF Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: Read/Write: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRFH OCRFL OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL. In addition to the use of OCRF as a 16-bit register with OCRFH as the upper 8 bits and OCRFL as the lower 8 bits, OCRFH and OCRFL can also be used as independent 8-bit registers. OCRFH and OCRFL can be read and written by the CPU, but when they are used in 16-bit mode, data transfer to and from the CPU is performed via a temporary register (TEMP). For details of TEMP, see 9.4.3, CPU Interface. OCRFH and OCRFL are each initialized to H'FF upon reset. a. 16-bit mode (OCRF) When CKSH2 is cleared to 0 in TCRF, OCRF operates as a 16-bit register. OCRF contents are constantly compared with TCF, and when both values match, CMFH is set to 1 in TCSRF. At the same time, IRRTFH is set to 1 in IRR2. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the CPU. Toggle output can be provided from the TMOFH pin by means of compare matches, and the output level can be set (high or low) by means of TOLH in TCRF. b. 8-bit mode (OCRFH/OCRFL) When CKSH2 is set to 1 in TCRF, OCRFH and OCRFL operate as two independent 8-bit registers. OCRFH contents are compared with TCFH, and OCRFL contents are with TCFL. When the OCRFH (OCRFL) and TCFH (TCFL) values match, CMFH (CMFL) is set to 1 in TCSRF. At the same time, IRRTFH (IRRTFL) is set to 1 in IRR2. If IENTFH (IENTFL) in IENR2 is 1 at this time, an interrupt request is sent to the CPU. Toggle output can be provided from the TMOFH pin (TMOFL pin) by means of compare matches, and the output level can be set (high or low) by means of TOLH (TOLL) in TCRF. 200 3. Timer control register F (TCRF) Bit: 7 TOLH 6 CKSH2 5 CKSH1 4 CKSH0 3 TOLL 2 CKSL2 1 CKSL1 0 CKSL0 Initial value: Read/Write: 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W TCRF is an 8-bit write-only register that switches between 16-bit mode and 8-bit mode, selects the input clock from among four internal clock sources or external event input, and sets the output level of the TMOFH and TMOFL pins. TCRF is initialized to H'00 upon reset. Bit 7: Toggle output level H (TOLH) Bit 7 sets the TMOFH pin output level. The output level is effective immediately after this bit is written. Bit 7 TOLH 0 1 Description Low level High level (initial value) Bits 6 to 4: Clock select H (CKSH2 to CKSH0) Bits 6 to 4 select the clock input to TCFH from among four internal clock sources or TCFL overflow. Bit 6 CKSH2 0 0 0 0 1 1 1 1 Bit 5 CKSH1 0 0 1 1 0 0 1 1 Bit 4 CKSH0 0 1 0 1 0 1 0 1 Not available Internal clock: counting on o/32 Internal clock: counting on o/16 Internal clock: counting on o/4 Internal clock: counting on ow/4 *: Don't care Description 16-bit mode, counting on TCFL overflow signal (initial value) 201 Bit 3: Toggle output level L (TOLL) Bit 3 sets the TMOFL pin output level. The output level is effective immediately after this bit is written. Bit 3 TOLL 0 1 Description Low level High level (initial value) Bits 2 to 0: Clock select L (CKSL2 to CKSL0) Bits 2 to 0 select the clock input to TCFL from among four internal clock sources or external event input. Bit 2 CKSL2 0 0 0 0 1 1 1 1 Note: Bit 1 CKSL1 0 0 1 1 0 0 1 1 Bit 0 CKSL0 0 1 0 1 0 1 0 1 Not available Internal clock: counting on o/32 Internal clock: counting on o/16 Internal clock: counting on o/4 Internal clock: counting on ow/4 Description Counting on external event (TMIF) rising/falling edge* 1 (initial value) *: Don't care 1. External event edge selection is set by IEG3 in the IRQ edge select register (IEGR). For details, see 1. IRQ edge select register (IEGR) in section 3.3.2. Note that the timer F counter may increment if the setting of IRQ3 in port mode register 1 (PMR1) is changed from 0 to 1 while the TMIF pin is low in order to change the TMIF pin function. 202 4. Timer control/status register F (TCSRF) Bit: Initial value: Read/Write: 7 OVFH 6 CMFH 5 OVIEH 4 CCLRH 3 OVFL 2 CMFL 1 OVIEL 0 CCLRL 0 R/(W)* 0 R/(W)* 0 R/W 0 R/W 0 R/(W)* 0 R/(W)* 0 R/W 0 R/W Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing. TCSRF is an 8-bit read/write register that performs counter clear selection, overflow flag setting, and compare match flag setting, and controls enabling of overflow interrupt requests. TCSRF is initialized to H'00 upon reset. Bit 7: Timer overflow flag H (OVFH) Bit 7 is a status flag indicating that TCFH has overflowed from H'FF to H'00. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 7 OVFH 0 1 Description Clearing conditions: After reading OVFH = 1, cleared by writing 0 to OVFH Setting conditions: Set when TCFH overflows from H'FF to H'00 (initial value) Bit 6: Compare match flag H (CMFH) Bit 6 is a status flag indicating that TCFH has matched OCRFH. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 6 CMFH 0 1 Description Clearing conditions: After reading CMFH = 1, cleared by writing 0 to CMFH Setting conditions: Set when the TCFH value matches the OCRFH value (initial value) 203 Bit 5: Timer overflow interrupt enable H (OVIEH) Bit 5 selects enabling or disabling of interrupt generation when TCFH overflows. Bit 5 OVIEH 0 1 Description TCFH overflow interrupt request is disabled TCFH overflow interrupt request is enabled (initial value) Bit 4: Counter clear H (CCLRH) In 8-bit mode, bit 4 selects whether TCF is cleared when TCF and OCRF match. In 8-bit mode, bit 4 selects whether TCFH is cleared when TCFH and OCRFH match. Bit 4 CCLRH 0 1 Description 16-bit mode: TCF clearing by compare match is disabled 8-bit mode: TCFH clearing by compare match is disabled 16-bit mode: TCF clearing by compare match is enabled 8-bit mode: TCFH clearing by compare match is enabled (initial value) Bit 3: Timer overflow flag L (OVFL) Bit 3 is a status flag indicating that TCFL has overflowed from H'FF to H'00. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 3 OVFL 0 1 Description Clearing conditions: After reading OVFL = 1, cleared by writing 0 to OVFL Setting conditions: Set when TCFL overflows from H'FF to H'00 (initial value) 204 Bit 2: Compare match flag L (CMFL) Bit 2 is a status flag indicating that TCFL has matched OCRFL. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 2 CMFL 0 1 Description Clearing conditions: After reading CMFL = 1, cleared by writing 0 to CMFL Setting conditions: Set when the TCFL value matches the OCRFL value (initial value) Bit 1: Timer overflow interrupt enable L (OVIEL) Bit 1 selects enabling or disabling of interrupt generation when TCFL overflows. Bit 1 OVIEL 0 1 Description TCFL overflow interrupt request is disabled TCFL overflow interrupt request is enabled (initial value) Bit 0: Counter clear L (CCLRL) Bit 0 selects whether TCFL is cleared when TCFL and OCRFL match. Bit 0 CCLRL 0 1 Description TCFL clearing by compare match is disabled TCFL clearing by compare match is enabled (initial value) 5. Clock stop register 1 (CKSTPR1) Bit 7 6 5 4 3 2 1 0 S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value Read/Write 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer F is described here. For details of the other bits, see the sections on the relevant modules. 205 Bit 2: Timer F module standby mode control (TFCKSTP) Bit 2 controls setting and clearing of module standby mode for timer F. TFCKSTP 0 1 Description Timer F is set to module standby mode Timer F module standby mode is cleared (initial value) 9.4.3 CPU Interface TCF and OCRF are 16-bit read/write registers, but the CPU is connected to the on-chip peripheral modules by an 8-bit data bus. When the CPU accesses these registers, it therefore uses an 8-bit temporary register (TEMP). In 16-bit mode, TCF read/write access and OCRF write access must be performed 16 bits at a time (using two consecutive byte-size MOV instructions), and the upper byte must be accessed before the lower byte. Data will not be transferred correctly if only the upper byte or only the lower byte is accessed. In 8-bit mode, there are no restrictions on the order of access. 206 1. Write access Write access to the upper byte results in transfer of the upper-byte write data to TEMP. Next, write access to the lower byte results in transfer of the data in TEMP to the upper register byte, and direct transfer of the lower-byte write data to the lower register byte. Figure 9-4 shows an example in which H'AA55 is written to TCF. Write to upper byte Module data bus CPU (H'AA) Bus interface TEMP (H'AA) TCFH ( ) TCFL ( ) Write to lower byte Module data bus CPU (H'55) Bus interface TEMP (H'AA) TCFH (H'AA) TCFL (H'55) Figure 9-4 Write Access to TCF (CPU TCF) 207 2. Read access In access to TCF, when the upper byte is read the upper-byte data is transferred directly to the CPU and the lower-byte data is transferred to TEMP. Next, when the lower byte is read, the lower-byte data in TEMP is transferred to the CPU. In access to OCRF, when the upper byte is read the upper-byte data is transferred directly to the CPU. When the lower byte is read, the lower-byte data is transferred directly to the CPU. Figure 9-5 shows an example in which TCF is read when it contains H'AAFF. Read upper byte Module data bus CPU (H'AA) Bus interface TEMP (H'FF) TCFH (H'AA) TCFL (H'FF) Read lower byte Module data bus CPU (H'FF) Bus interface TEMP (H'FF) TCFH (AB)* TCFL (00)* Note: * H'AB00 if counter has been updated once. Figure 9-5 Read Access to TCF (TCF CPU) 208 9.4.4 Operation Timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is constantly compared with the value set in output compare register F, and the counter can be cleared, an interrupt requested, or port output toggled, when the two values match. Timer F can also function as two independent 8-bit timers. 1. Timer F operation Timer F has two operating modes, 16-bit timer mode and 8-bit timer mode. The operation in each of these modes is described below. a. Operation in 16-bit timer mode When CKSH2 is cleared to 0 in timer control register F (TCRF), timer F operates as a 16bit timer. Following a reset, timer counter F (TCF) is initialized to H'0000, output compare register F (OCRF) to H'FFFF, and timer control register F (TCRF) and timer control/status register F (TCSRF) to H'00. The counter starts incrementing on external event (TMIF) input. The external event edge selection is set by IEG3 in the IRQ edge select register (IEGR). The timer F operating clock can be selected from four internal clocks output by prescaler S or an external clock by means of bits CKSL2 to CKSL0 in TCRF. OCRF contents are constantly compared with TCF, and when both values match, CMFH is set to 1 in TCSRF. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the CPU, and at the same time, TMOFH pin output is toggled. If CCLRH in TCSRF is 1, TCF is cleared. TMOFH pin output can also be set by TOLH in TCRF. When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in TCSRF and IENTFH in IENR2 are both 1, an interrupt request is sent to the CPU. b. Operation in 8-bit timer mode When CKSH2 is set to 1 in TCRF, TCF operates as two independent 8-bit timers, TCFH and TCFL. The TCFH/TCFL input clock is selected by CKSH2 to CKSH0/CKSL2 to CKSL0 in TCRF. When the OCRFH/OCRFL and TCFH/TCFL values match, CMFH/CMFL is set to 1 in TCSRF. If IENTFH/IENTFL in IENR2 is 1, an interrupt request is sent to the CPU, and at the same time, TMOFH pin/TMOFL pin output is toggled. If CCLRH/CCLRL in TCSRF is 1, TCFH/TCFL is cleared. TMOFH pin/TMOFL pin output can also be set by TOLH/TOLL in TCRF. When TCFH/TCFL overflows from H'FF to H'00, OVFH/OVFL is set to 1 in TCSRF. If OVIEH/OVIEL in TCSRF and IENTFH/IENTFL in IENR2 are both 1, an interrupt request is sent to the CPU. 209 2. TCF increment timing TCF is incremented by clock input (internal clock or external event input). a. Internal clock operation Bits CKSH2 to CKSH0 or CKSL2 to CKSL0 in TCRF select one of four internal clock sources (o/32, o/16, o/4, or ow/4) created by dividing the system clock (o or ow). b. External event operation External event input is selected by clearing CKSL2 to 0 in TCRF. TCF can increment on either the rising or falling edge of external event input. External event edge selection is set by IEG3 in the interrupt controller's IEGR register. An external event pulse width of at least 2 system clocks (o) is necessary. Shorter pulses will not be counted correctly. 3. TMOFH/TMOFL output timing In TMOFH/TMOFL output, the value set in TOLH/TOLL in TCRF is output. The output is toggled by the occurrence of a compare match. Figure 9-6 shows the output timing. o TMIF (when IEG3 = 1) Count input clock TCF N N+1 N N+1 OCRF N N Compare match signal TMOFH TMOFL Figure 9-6 TMOFH/TMOFL Output Timing 210 4. TCF clear timing TCF can be cleared by a compare match with OCRF. 5. Timer overflow flag (OVF) set timing OVF is set to 1 when TCF overflows from H'FFFF to H'0000. 6. Compare match flag set timing The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match. The compare match signal is generated in the last state during which the values match (when TCF is updated from the matching value to a new value). When TCF matches OCRF, the compare match signal is not generated until the next counter clock. 7. Timer F operation modes Timer F operation modes are shown in table 9-10. Table 9-10 Timer F Operation Modes Operation Mode TCF OCRF TCRF TCSRF Module Standby Halted Held Held Held Reset Reset Reset Reset Reset Active Functions Functions Functions Functions Sleep Functions Held Held Held Watch Subactive Subsleep Standby Functions/ Functions/ Functions/ Halted Halted* Halted* Halted* Held Held Held Functions Functions Functions Held Held Held Held Held Held Note: * When o w /4 is selected as the TCF internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. This results in a maximum count cycle error of 1/o (s). When the counter is operated in subactive mode, watch mode, or subsleep mode, ow /4 must be selected as the internal clock. The counter will not operate if any other internal clock is selected. 211 9.4.5 Application Notes The following types of contention and operation can occur when timer F is used. 1. 16-bit timer mode In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match signal is generated. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write. TMOFL pin output is unstable in 16-bit mode, and should not be used; the TMOFL pin should be used as a port pin. If an OCRFL write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, if the written data and the counter value match, a compare match signal will be generated at that point. As the compare match signal is output in synchronization with the TCFL clock, a compare match will not result in compare match signal generation if the clock is stopped. Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated. Compare match flag CMFL is set if the setting conditions for the lower 8 bits are satisfied. When TCF overflows, OVFH is set. OVFL is set if the setting conditions are satisfied when the lower 8 bits overflow. If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not output. 2. 8-bit timer mode a. TCFH, OCRFH In toggle output, TMOFH pin output is toggled when a compare match occurs. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write. If an OCRFH write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, if the written data and the counter value match, a compare match signal will be generated at that point. The compare match signal is output in synchronization with the TCFH clock. If a TCFH write and overflow signal output occur simultaneously, the overflow signal is not output. b. TCFL, OCRFL In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLL data is output to the TMOFL pin as a result of the TCRF write. 212 If an OCRFL write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, if the written data and the counter value match, a compare match signal will be generated at that point. As the compare match signal is output in synchronization with the TCFL clock, a compare match will not result in compare match signal generation if the clock is stopped. If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not output. 3. Clear timer FH, timer FL interrupt request flags (IRRTFH, IRRTFL), timer overflow flags H, L (OVFH, OVFL) and compare match flags H, L (CMFH, CMFL) When ow/4 is selected as the internal clock, "Interrupt factor generation signal" will be operated with ow and the signal will be outputted with ow width. And, "Overflow signal" and "Compare match signal" are controlled with 2 cycles of ow signals. Those signals are outputted with 2 cycles width of ow (figure 9-7) In active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the term of validity of "Interrupt factor generation signal", same interrupt request flag is set. (figure 97 1) And, you cannot be cleared timer overflow flag and compare match flag during the term of validity of "Overflow signal" and "Compare match signal". For interrupt request flag is set right after interrupt request is cleared, interrupt process to one time timer FH, timer FL interrupt might be repeated. (figure 9-7 2) Therefore, to definitely clear interrupt request flag in active (high-speed, medium-speed) mode, clear should be processed after the time that calculated with below (1) formula. And, to definitely clear timer overflow flag and compare match flag, clear should be processed after read timer control status register F (TCSRF) after the time that calculated with below (1) formula. For ST of (1) formula, please substitute the longest number of execution states in used instruction. (10 states of RTE instruction when MULXU, DIVXU instruction is not used, 14 states when MULXU, DIVXU instruction is used) In subactive mode, there are not limitation for interrupt request flag, timer overflow flag, and compare match flag clear. The term of validity of "Interrupt factor generation signal" = 1 cycle of ow + waiting time for completion of executing instruction + interrupt time synchronized with o = 1/ow + ST x (1/o) + (2/o) (second).....(1) ST: Executing number of execution states Method 1 is recommended to operate for time efficiency. Method 1 1. Prohibit interrupt in interrupt handling routine (set IENFH, IENFL to 0). 2. After program process returned normal handling, clear interrupt request flags (IRRTFH, IRRTFL) after more than that calculated with (1) formula. 213 3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH, OVFL) and compare match flags (CMFH, CMFL). 4. Operate interrupt permission (set IENFH, IENFL to 1). Method 2 1. Set interrupt handling routine time to more than time that calculated with (1) formula. 2. Clear interrupt request flags (IRRTFH, IRRTFL) at the end of interrupt handling routine. 3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH, OVFL) and compare match flags (CMFH, CMFL). All above attentions are also applied in 16-bit mode and 8-bit mode. Interrupt request flag clear 2 Interrupt request flag clear Normal Program process Interrupt Interrupt ow Interrupt factor generation signal (Internal signal, nega-active) Overflow signal, Compare match signal (Internal signal, nega-active) Interrupt request flag (IRRTFH, IRRTFL) 1 Figure 9-7 Clear Interrupt Request Flag when Interrupt Factor Generation Signal is Valid 4. Timer counter (TCF) read/write When ow/4 is selected as the internal clock in active (high-speed, medium-speed) mode, write on TCF is impossible. And, when read TCF, as the system clock and internal clock are mutually asynchronous, TCF synchronizes with synchronization circuit. This results in a maximum TCF read value error of 1. When read/write TCF in active (high-speed, medium-speed) mode is needed, please select internal clock except for ow/4 before read/write. In subactive mode, even ow/4 is selected as the internal clock, normal read/write TCF is possible. 214 9.5 9.5.1 Timer G Overview Timer G is an 8-bit timer with dedicated input capture functions for the rising/falling edges of pulses input from the input capture input pin (input capture input signal). High-frequency component noise in the input capture input signal can be eliminated by a noise canceler, enabling accurate measurement of the input capture input signal duty cycle. If input capture input is not set, timer G functions as an 8-bit interval timer. 1. Features Features of timer G are given below. * Choice of four internal clock sources (o/64, o/32, o/2, ow/2) * Dedicated input capture functions for rising and falling edges * Level detection at counter overflow It is possible to detect whether overflow occurred when the input capture input signal was high or when it was low. * Selection of whether or not the counter value is to be cleared at the input capture input signal rising edge, falling edge, or both edges * Two interrupt sources: one input capture, one overflow. The input capture input signal rising or falling edge can be selected as the interrupt source. * A built-in noise canceler eliminates high-frequency component noise in the input capture input signal. * Watch mode, subactive mode and subsleep mode operation is possible when ow/2 is selected as the internal clock. * Use of module standby mode enables this module to be placed in standby mode independently when not used. 215 2. Block diagram Figure 9-8 shows a block diagram of timer G. o PSS TMG ow/4 ICRGF TMIG Noise canceler Edge detector TCG NCS ICRGR IRRTG Notation: TMG TCG : Timer mode register G : Timer counter G ICRGF : Input capture register GF ICRGR : Input capture register GR IRRTG : Timer G interrupt request flag NCS PSS : Noise canceler select : Prescaler S Figure 9-8 Block Diagram of Timer G 216 Internal data bus Level detector 3. Pin configuration Table 9-11 shows the timer G pin configuration. Table 9-11 Pin Configuration Name Input capture input Abbrev. TMIG I/O Input Function Input capture input pin 4. Register configuration Table 9-12 shows the register configuration of timer G. Table 9-12 Timer G Registers Name Timer control register G Timer counter G Input capture register GF Input capture register GR Clock stop register 1 Abbrev. TMG TCG ICRGF ICRGR CKSTPR1 R/W R/W -- R R R/W Initial Value H'00 H'00 H'00 H'00 H'FF Address H'FFBC -- H'FFBD H'FFBE H'FFFA 9.5.2 Register Descriptions 1. Timer counter (TCG) Bit: Initial value: Read/Write: 7 TCG7 6 TCG6 5 TCG5 4 TCG4 3 TCG3 2 TCG2 1 TCG1 0 TCG0 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- TCG is an 8-bit up-counter which is incremented by clock input. The input clock is selected by bits CKS1 and CKS0 in TMG. TMIG in PMR1 is set to 1 to operate TCG as an input capture timer, or cleared to 0 to operate TCG as an interval timer*. In input capture timer operation, the TCG value can be cleared by the rising edge, falling edge, or both edges of the input capture input signal, according to the setting made in TMG. When TCG overflows from H'FF to H'00, if OVIE in TMG is 1, IRRTG is set to 1 in IRR2, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU. For details of the interrupt, see 3.3, Interrupts. 217 TCG cannot be read or written by the CPU. It is initialized to H'00 upon reset. Note: * An input capture signal may be generated when TMIG is modified. 2. Input capture register GF (ICRGF) Bit: Initial value: Read/Write: 7 ICRGF7 6 ICRGF6 5 ICRGF5 4 ICRGF4 3 ICRGF3 2 ICRGF2 1 ICRGF1 0 ICRGF0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time, IRRTG is set to 1 in IRR2, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU. For details of the interrupt, see 3.3, Interrupts. To ensure dependable input capture operation, the pulse width of the input capture input signal must be at least 2o or 2oSUB (when the noise canceler is not used). ICRGF is initialized to H'00 upon reset. 3. Input capture register GR (ICRGR) Bit: Initial value: Read/Write: 7 ICRGR7 6 ICRGR6 5 ICRGR5 4 ICRGR4 3 ICRGR3 2 ICRGR2 1 ICRGR1 0 ICRGR0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ICRGR is an 8-bit read-only register. When a rising edge of the input capture input signal is detected, the current TCG value is transferred to ICRGR. If IIEGS in TMG is 1 at this time, IRRTG is set to 1 in IRR2, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU. For details of the interrupt, see 3.3, Interrupts. To ensure dependable input capture operation, the pulse width of the input capture input signal must be at least 2o or 2oSUB (when the noise canceler is not used). ICRGR is initialized to H'00 upon reset. 218 4. Timer mode register G (TMG) Bit: Initial value: Read/Write: 7 OVFH 6 OVFL 5 OVIE 4 IIEGS 3 CCLR1 2 CCLR0 1 CKS1 0 CKS0 0 R/(W)* 0 R/(W)* 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Note: * Bits 7 and 6 can only be written with 0, for flag clearing. TMG is an 8-bit read/write register that performs TCG clock selection from four internal clock sources, counter clear selection, and edge selection for the input capture input signal interrupt request, controls enabling of overflow interrupt requests, and also contains the overflow flags. TMG is initialized to H'00 upon reset. Bit 7: Timer overflow flag H (OVFH) Bit 7 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture input signal is high. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 7 OVFH 0 1 Description Clearing conditions: After reading OVFH = 1, cleared by writing 0 to OVFH Setting conditions: Set when TCG overflows from H'FF to H'00 (initial value) Bit 6: Timer overflow flag L (OVFL) Bit 6 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture input signal is low, or in interval operation. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 6 OVFL 0 1 Description Clearing conditions: After reading OVFL = 1, cleared by writing 0 to OVFL Setting conditions: Set when TCG overflows from H'FF to H'00 (initial value) 219 Bit 5: Timer overflow interrupt enable (OVIE) Bit 5 selects enabling or disabling of interrupt generation when TCG overflows. Bit 5 OVIE 0 1 Description TCG overflow interrupt request is disabled TCG overflow interrupt request is enabled (initial value) Bit 4: Input capture interrupt edge select (IIEGS) Bit 4 selects the input capture input signal edge that generates an interrupt request. Bit 4 IIEGS 0 1 Description Interrupt generated on rising edge of input capture input signal Interrupt generated on falling edge of input capture input signal (initial value) Bits 3 and 2: Counter clear 1 and 0 (CCLR1, CCLR0) Bits 3 and 2 specify whether or not TCG is cleared by the rising edge, falling edge, or both edges of the input capture input signal. Bit 3 CCLR1 0 0 1 1 Bit 2 CCLR0 0 1 0 1 Description TCG clearing is disabled TCG cleared by falling edge of input capture input signal TCG cleared by rising edge of input capture input signal TCG cleared by both edges of input capture input signal (initial value) Bits 1 and 0: Clock select (CKS1, CKS0) Bits 1 and 0 select the clock input to TCG from among four internal clock sources. Bit 1 CKS1 0 0 1 1 Bit 0 CKS0 0 1 0 1 Description Internal clock: counting on o/64 Internal clock: counting on o/32 Internal clock: counting on o/2 Internal clock: counting on ow/4 (initial value) 220 5. Clock stop register 1 (CKSTPR1) Bit 7 6 5 4 3 2 1 0 S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value Read/Write 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer G is described here. For details of the other bits, see the sections on the relevant modules. Bit 3: Timer G module standby mode control (TGCKSTP) Bit 3 controls setting and clearing of module standby mode for timer G. TGCKSTP 0 1 Description Timer G is set to module standby mode Timer G module standby mode is cleared (initial value) 9.5.3 Noise Canceler The noise canceler consists of a digital low-pass filter that eliminates high-frequency component noise from the pulses input from the input capture input pin. The noise canceler is set by NCS* in PMR3. Figure 9-9 shows a block diagram of the noise canceler. Sampling clock Input capture input signal D C Q Latch D C Q Latch D C Q Latch D C Q Latch D C Q Latch Match detector Noise canceler output t Sampling clock t: Set by CKS1 and CKS0 Figure 9-9 Noise Canceler Block Diagram 221 The noise canceler consists of five latch circuits connected in series and a match detector circuit. When the noise cancellation function is not used (NCS = 0), the system clock is selected as the sampling clock When the noise cancellation function is used (NCS = 1), the sampling clock is the internal clock selected by CKS1 and CKS0 in TMG, the input capture input is sampled on the rising edge of this clock, and the data is judged to be correct when all the latch outputs match. If all the outputs do not match, the previous value is retained. After a reset, the noise canceler output is initialized when the falling edge of the input capture input signal has been sampled five times. Therefore, after making a setting for use of the noise cancellation function, a pulse with at least five times the width of the sampling clock is a dependable input capture signal. Even if noise cancellation is not used, an input capture input signal pulse width of at least 2o or 2o SUB is necessary to ensure that input capture operations are performed properly Note: * An input capture signal may be generated when the NCS bit is modified. Figure 9-10 shows an example of noise canceler timing. In this example, high-level input of less than five times the width of the sampling clock at the input capture input pin is eliminated as noise. Input capture input signal Sampling clock Noise canceler output Eliminated as noise Figure 9-10 Noise Canceler Timing (Example) 222 9.5.4 Operation Timer G is an 8-bit timer with built-in input capture and interval functions. 1. Timer G functions Timer G is an 8-bit up-counter with two functions, an input capture timer function and an interval timer function. The operation of these two functions is described below. a. Input capture timer operation When the TMIG bit is set to 1 in port mode register 1 (PMR1), timer G functions as an input capture timer*. In a reset, timer mode register G (TMG), timer counter G (TCG), input capture register GF (ICRGF), and input capture register GR (ICRGR) are all initialized to H'00. Following a reset, TCG starts incrementing on the o/64 internal clock. The input clock can be selected from four internal clock sources by bits CKS1 and CKS0 in TMG. When a rising edge/falling edge is detected in the input capture signal input from the TMIG pin, the TCG value at that time is transferred to ICRGR/ICRGF. When the edge selected by IIEGS in TMG is input, IRRTG is set to 1 in IRR2, and if the IENTG bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU. For details of the interrupt, see 3.3., Interrupts. TCG can be cleared by a rising edge, falling edge, or both edges of the input capture signal, according to the setting of bits CCLR1 and CCLR0 in TMG. If TCG overflows when the input capture signal is high, the OVFH bit is set in TMG; if TCG overflows when the input capture signal is low, the OVFL bit is set in TMG. If the OVIE bit in TMG is 1 when these bits are set, IRRTG is set to 1 in IRR2, and if the IENTG bit in IENR2 is 1, timer G sends an interrupt request to the CPU. For details of the interrupt, see 3.3., Interrupts. Timer G has a built-in noise canceler that enables high-frequency component noise to be eliminated from pulses input from the TMIG pin. For details, see 9.5.3, Noise Canceler. Note: * An input capture signal may be generated when TMIG is modified. b. Interval timer operation When the TMIG bit is cleared to 0 in PMR1, timer G functions as an interval timer. Following a reset, TCG starts incrementing on the o/64 internal clock. The input clock can be selected from four internal clock sources by bits CKS1 and CKS0 in TMG. TCG increments on the selected clock, and when it overflows from H'FF to H'00, the OVFL bit is set to 1 in TMG. If the OVIE bit in TMG is 1 at this time, IRRTG is set to 1 in IRR2, and if the IENTG bit in IENR2 is 1, timer G sends an interrupt request to the CPU. For details of the interrupt, see 3.3., Interrupts. 223 2. Increment timing TCG is incremented by internal clock input. Bits CKS1 and CKS0 in TMG select one of four internal clock sources (o/64, o/32, o/2, or ow/4) created by dividing the system clock (o) or watch clock (ow). 3. Input capture input timing a. Without noise cancellation function For input capture input, dedicated input capture functions are provided for rising and falling edges. Figure 9-11 shows the timing for rising/falling edge input capture input. Input capture input signal Input capture signal F Input capture signal R Figure 9-11 Input Capture Input Timing (without Noise Cancellation Function) b. With noise cancellation function When noise cancellation is performed on the input capture input, the passage of the input capture signal through the noise canceler results in a delay of five sampling clock cycles from the input capture input signal edge. 224 Figure 9-12 shows the timing in this case. Input capture input signal Sampling clock Noise canceler output Input capture signal R Figure 9-12 Input Capture Input Timing (with Noise Cancellation Function) 4. Timing of input capture by input capture input Figure 9-13 shows the timing of input capture by input capture input Input capture signal TCG N-1 N N+1 Input capture register H'XX N Figure 9-13 Timing of Input Capture by Input Capture Input 225 5. TGC clear timing TCG can be cleared by the rising edge, falling edge, or both edges of the input capture input signal. Figure 9-14 shows the timing for clearing by both edges. Input capture input signal Input capture signal F Input capture signal R TCG N H'00 N H'00 Figure 9-14 TCG Clear Timing 226 6. Timer G operation modes Timer G operation modes are shown in table 9-13. Table 9-13 Timer G Operation Modes Module Subactive Subsleep Standby Standby Halted Halted Held Held Held Operation Mode TCG Input capture Interval ICRGF ICRGR TMG Reset Active Sleep Watch Reset Functions* Functions* Functions/ Functions/ Functions/ Halted halted* halted* halted* Reset Functions* Functions* Functions/ Functions/ Functions/ Halted halted* halted* halted* Reset Functions* Functions* Functions/ Functions/ Functions/ Held halted* halted* halted* Reset Functions* Functions* Functions/ Functions/ Functions/ Held halted* halted* halted* Reset Functions Held Held Functions Held Held Note: * When ow/4 is selected as the TCG internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. This results in a maximum count cycle error of 1/o(s). When ow/4 is selected as the TCG internal clock in watch mode, TCG and the noise canceler operate on the ow/4 internal clock without regard to the o subclock (ow/8, ow/4, ow/2). Note that when another internal clock is selected, TCG and the noise canceler do not operate, and input of the input capture input signal does not result in input capture. To operate the timer G in subactive mode or subsleep mode, select ow/4 as the TCG internal clock and ow/2 as the subclock o SUB. Note that when other internal clock is selected, or when ow/8 or ow/4 is selected as the subclock o SUB, TCG and the noise canceler do not operate. 9.5.5 Application Notes 1. Internal clock switching and TCG operation Depending on the timing, TCG may be incremented by a switch between difference internal clock sources. Table 9-14 shows the relation between internal clock switchover timing (by write to bits CKS1 and CKS0) and TCG operation. When TCG is internally clocked, an increment pulse is generated on detection of the falling edge of an internal clock signal, which is divided from the system clock (o) or subclock (ow). For this reason, in a case like No. 3 in table 9-14 where the switch is from a high clock signal to a low clock signal, the switchover is seen as a falling edge, causing TCG to increment. 227 Table 9-14 Internal Clock Switching and TCG Operation No. 1 Clock Levels Before and After Modifying Bits CKS1 and CKS0 Goes from low level to low level TCG Operation Clock before switching Clock after switching Count clock TCG N N+1 Write to CKS1 and CKS0 2 Goes from low level to high level Clock before switching Clock before switching Count clock TCG N N+1 N+2 Write to CKS1 and CKS0 3 Goes from high level to low level Clock before switching Clock before switching * Count clock TCG N N+1 N+2 Write to CKS1 and CKS0 228 No. 4 Clock Levels Before and After Modifying Bits CKS1 and CKS0 Goes from high level to high level TCG Operation Clock before switching Clock before switching Count clock TCG N N+1 N+2 Write to CKS1 and CKS0 Note: * The switchover is seen as a falling edge, and TCG is incremented. 2. Notes on port mode register modification The following points should be noted when a port mode register is modified to switch the input capture function or the input capture input noise canceler function. * Switching input capture input pin function Note that when the pin function is switched by modifying TMIG in port mode register 1 (PMR1), which performs input capture input pin control, an edge will be regarded as having been input at the pin even though no valid edge has actually been input. Input capture input signal input edges, and the conditions for their occurrence, are summarized in table 9-15. 229 Table 9-15 Input Capture Input Signal Input Edges Due to Input Capture Input Pin Switching, and Conditions for Their Occurrence Input Capture Input Signal Input Edge Generation of rising edge Conditions When TMIG is modified from 0 to 1 while the TMIG pin is high When NCS is modified from 0 to 1 while the TMIG pin is high, then TMIG is modified from 0 to 1 before the signal is sampled five times by the noise canceler Generation of falling edge When TMIG is modified from 1 to 0 while the TMIG pin is high When NCS is modified from 0 to 1 while the TMIG pin is low, then TMIG is modified from 0 to 1 before the signal is sampled five times by the noise canceler When NCS is modified from 0 to 1 while the TMIG pin is high, then TMIG is modified from 1 to 0 after the signal is sampled five times by the noise canceler Note: When the P13 pin is not set as an input capture input pin, the timer G input capture input signal is low. * Switching input capture input noise canceler function When performing noise canceler function switching by modifying NCS in port mode register 3 (PMR3), which controls the input capture input noise canceler, TMIG should first be cleared to 0. Note that if NCS is modified without first clearing TMIG, an edge will be regarded as having been input at the pin even though no valid edge has actually been input. Input capture input signal input edges, and the conditions for their occurrence, are summarized in table 9-16. Table 9-16 Input Capture Input Signal Input Edges Due to Noise Canceler Function Switching, and Conditions for Their Occurrence Input Capture Input Signal Input Edge Generation of rising edge Conditions When the TMIG pin level is switched from low to high while TMIG is set to 1, then NCS is modified from 0 to 1 before the signal is sampled five times by the noise canceler When the TMIG pin level is switched from high to low while TMIG is set to 1, then NCS is modified from 1 to 0 before the signal is sampled five times by the noise canceler Generation of falling edge 230 When the pin function is switched and an edge is generated in the input capture input signal, if this edge matches the edge selected by the input capture interrupt select (IIEGS) bit, the interrupt request flag will be set to 1. The interrupt request flag should therefore be cleared to 0 before use. Figure 9-15 shows the procedure for port mode register manipulation and interrupt request flag clearing. When switching the pin function, set the interrupt-disabled state before manipulating the port mode register, then, after the port mode register operation has been performed, wait for the time required to confirm the input capture input signal as an input capture signal (at least two system clocks when the noise canceler is not used; at least five sampling clocks when the noise canceler is used), before clearing the interrupt enable flag to 0. There are two ways of preventing interrupt request flag setting when the pin function is switched: by controlling the pin level so that the conditions shown in tables 9-16 and 9-17 are not satisfied, or by setting the opposite of the generated edge in the IIEGS bit in TMG. Disable interrupts. (Interrupts can also be disabled by manipulating the interrupt enable bit in interrupt enable register 2.) After manipulating he port mode register, wait for the TMIG confirmation time (at least two system clocks when the noise canceler is not used; at least five sampling clocks when the noise canceler is used), then clear the interrupt enable flag to 0. Set I bit to 1 in CCR Manipulate port mode register TMIG confirmation time Clear interrupt request flag to 0 Clear I bit to 0 in CCR Enable interrupts Figure 9-15 Port Mode Register Manipulation and Interrupt Enable Flag Clearing Procedure 231 9.5.6 Timer G Application Example Using timer G, it is possible to measure the high and low widths of the input capture input signal as absolute values. For this purpose, CCLR1 and CCLR0 should both be set to 1 in TMG. Figure 9-16 shows an example of the operation in this case. Input capture input signal H'FF Input capture register GF Input capture register GR H'00 TCG Counter cleared Figure 9-16 Timer G Application Example 232 9.6 9.6.1 Watchdog Timer Overview The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset the chip internally. 1. Features Features of the watchdog timer are given below. * Incremented by internal clock source (o/8192 or ow/32). * A reset signal is generated when the counter overflows. The overflow period can be set from from 1 to 256 times 8192/o or 32/ow (from approximately 4 ms to 1000 ms when o = 2.00 MHz). * Use of module standby mode enables this module to be placed in standby mode independently when not used. 2. Block diagram Figure 9-17 shows a block diagram of the watchdog timer. ow/32 TCSRW Internal data bus Reset signal 233 o PSS o/8192 TCW Notation: TCSRW: Timer control/status register W Timer counter W TCW: Prescaler S PSS: Figure 9-17 Block Diagram of Watchdog Timer 3. Register configuration Table 9-17 shows the register configuration of the watchdog timer. Table 9-17 Watchdog Timer Registers Name Timer control/status register W Timer counter W Clock stop register 2 Port mode register 3 Abbrev. TCSRW TCW CKSTP2 PMR3 R/W R/W R/W R/W R/W Initial Value H'AA H'00 H'FF H'00 Address H'FFB2 H'FFB3 H'FFFB H'FFCA 9.6.2 Register Descriptions 1. Timer control/status register W (TCSRW) Bit Initial value Read/Write 7 B6WI 1 R 6 TCWE 0 R/W * 5 B4WI 1 R 4 TCSRWE 0 R/W * 3 B2WI 1 R 2 WDON 0 R/W* 1 B0WI 1 R 0 WRST 0 R/W * Note: * Write is permitted only under certain conditions, which are given in the descriptions of the individual bits. TCSRW is an 8-bit read/write register that controls write access to TCW and TCSRW itself, controls watchdog timer operations, and indicates operating status. Bit 7: Bit 6 write inhibit (B6WI) Bit 7 controls the writing of data to bit 6 in TCSRW. Bit 7 B6WI 0 1 Description Bit 6 is write-enabled Bit 6 is write-protected (initial value) This bit is always read as 1. Data written to this bit is not stored. 234 Bit 6: Timer counter W write enable (TCWE) Bit 6 controls the writing of data to TCW. Bit 6 TCWE 0 1 Description Data cannot be written to TCW Data can be written to TCW (initial value) Bit 5: Bit 4 write inhibit (B4WI) Bit 5 controls the writing of data to bit 4 in TCSRW. Bit 5 B4WI 0 1 Description Bit 4 is write-enabled Bit 4 is write-protected (initial value) This bit is always read as 1. Data written to this bit is not stored. Bit 4: Timer control/status register W write enable (TCSRWE) Bit 4 controls the writing of data to TCSRW bits 2 and 0. Bit 4 TCSRWE 0 1 Description Data cannot be written to bits 2 and 0 Data can be written to bits 2 and 0 (initial value) Bit 3: Bit 2 write inhibit (B2WI) Bit 3 controls the writing of data to bit 2 in TCSRW. Bit 3 B2WI 0 1 Description Bit 2 is write-enabled Bit 2 is write-protected (initial value) This bit is always read as 1. Data written to this bit is not stored. 235 Bit 2: Watchdog timer on (WDON) Bit 2 enables watchdog timer operation. Bit 2 WDON 0 Description Watchdog timer operation is disabled Clearing conditions: Reset, or when TCSRWE = 1 and 0 is written in both B2WI and WDON Watchdog timer operation is enabled Setting conditions: When TCSRWE = 1 and 0 is written in B2WI and 1 is written in WDON (initial value) 1 Counting starts when this bit is set to 1, and stops when this bit is cleared to 0. Bit 1: Bit 0 write inhibit (B0WI) Bit 1 controls the writing of data to bit 0 in TCSRW. Bit 1 B0WI 0 1 Description Bit 0 is write-enabled Bit 0 is write-protected (initial value) This bit is always read as 1. Data written to this bit is not stored. Bit 0: Watchdog timer reset (WRST) Bit 0 indicates that TCW has overflowed, generating an internal reset signal. The internal reset signal generated by the overflow resets the entire chip. WRST is cleared to 0 by a reset from the RES pin, or when software writes 0. Bit 0 WRST 0 Description Clearing conditions: Reset by RES pin When TCSRWE = 1, and 0 is written in both B0WI and WRST Setting conditions: When TCW overflows and an internal reset signal is generated 1 236 2. Timer counter W (TCW) Bit Initial value Read/Write 7 TCW7 0 R/W 6 TCW6 0 R/W 5 TCW5 0 R/W 4 TCW4 0 R/W 3 TCW3 0 R/W 2 TCW2 0 R/W 1 TCW1 0 R/W 0 TCW0 0 R/W TCW is an 8-bit read/write up-counter, which is incremented by internal clock input. The input clock is o/8192 or ow/32. The TCW value can always be written or read by the CPU. When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to 1 in TCSRW. Upon reset, TCW is initialized to H'00. 3. Clock stop register 2 (CKSTPR2) Bit 7 -- 6 -- 5 -- 4 -- 3 2 1 0 AECKSTP WDCKSTP PWCKSTP LDCKSTP Initial value Read/Write 1 -- 1 -- 1 -- 1 -- 1 R/W 1 R/W 1 R/W 1 R/W CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to the watchdog timer is described here. For details of the other bits, see the sections on the relevant modules. Bit 2: Watchdog timer module standby mode control (WDCKSTP) Bit 2 controls setting and clearing of module standby mode for the watchdog timer. WDCKSTP 0 1 Description Watchdog timer is set to module standby mode Watchdog timer module standby mode is cleared (initial value) Note: WDCKSTP is valid when the WDON bit is cleared to 0 in timer control/status register W (TCSRW). If WDCKSTP is set to 0 while WDON is set to 1 (during watchdog timer operation), 0 will be set in WDCKSTP but the watchdog timer will continue its watchdog function and will not enter modulep standby mode. When the watchdog function ends and WDON is cleared to 0 by software, the WDCKSTP setting will become valid and the watchdog timer will enter module standby mode. 237 4. Port mode register 3 (PMR3) PMR3 is an 8-bit read/write register, mainly controlling the selection of pin functions for port 3 pins. Only the bit relating to the watchdog timer is described here. For details of the other bits, see section 8, I/O Ports. Bit 5: Watchdog timer source clock select (WDCKS) WDCKS 0 1 Description o/8192 selected ow/32 selected (initial value) Note: WDCKS can be set when WDON has been cleared to 0. 9.6.3 Timer Operation The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input (o/8192 or ow/32). The input clock is selected by bit WDCKS in port mode register 3 (PMR3): o/8192 is selected when WDCKS is cleared to 0, and ow/32 when set to 1. When TCSRWE = 1 in TCSRW, if 0 is written in B2WI and 1 is simultaneously written in WDON, TCW starts counting up. When the TCW count value reaches H'FF, the next clock input causes the watchdog timer to overflow, and an internal reset signal is generated one base clock (o or oSUB) cycle later. The internal reset signal is output for 512 clock cycles of the oOSC clock. It is possible to write to TCW, causing TCW to count up from the written value. The overflow period can be set in the range from 1 to 256 input clocks, depending on the value written in TCW. 238 Figure 9-18 shows an example of watchdog timer operations. Example: o = 2 MHz and the desired overflow period is 30 ms. 2 x 106 x 30 x 10-3 = 7.3 8192 The value set in TCW should therefore be 256 - 8 = 248 (H'F8). H'FF H'F8 TCW count value TCW overflow H'00 Start H'F8 written in TCW Internal reset signal 512 oOSC clock cycles H'F8 written in TCW Reset Figure 9-18 Typical Watchdog Timer Operations (Example) 9.6.4 Watchdog Timer Operation States Table 9-18 summarizes the watchdog timer operation states. Table 9-18 Watchdog Timer Operation States Operation Mode TCW TCSRW Module Standby Halted Retained Reset Reset Reset Active Functions Functions Sleep Watch Subactive Subsleep Standby Functions/ Halted Halted* Functions/ Retained Halted* Halted Retained Functions Halted Functions Retained Note: * Functions when ow/32 is selected as the input clock. 239 240 Section 10 Serial Communication Interface 10.1 Overview The H8/3937 Series and H8/3937R Series are provided with two serial communication interface (SCI) channels plus one SCI channel for on-chip FLEXTM decoder interfacing. The functions of the three SCI channels are summarized in table 10-1. Table 10-1 Overview of SCI Functions SCI Name Functions SCI1 (Internal function) SCI31, SCI32 Synchronous serial transfer functions * Choice of transfer data length (8 or 16 bits) * Continuous clock output function Synchronous serial transfer functions * 8-bit transfer data length * Transmission/reception/simultaneous transmission and reception Asynchronous serial transfer functions * Multiprocessor communication function * Choice of transfer data length (5 or 7 or 8 bits) * Choice of stop bit length (1 or 2 bits) * Parity addition function Features * Choice of 8 internal clocks (o/1024 to o/4, oW/4) or external clock * Interrupt generated on completion of transfer * On-chip baud rate generator * Receive error detection * Break detection * Interrupt generated on completion of transfer or in case of error 241 10.2 10.2.1 SCI1 [Chip Internal Function] Overview Serial communication interface 1 (SCI1) can carry out 8-bit or 16-bit serial data transfer in synchronous mode. SCI1 is an internal function that performs interfacing to the FLEXTM decoder incorporated in the chip. It cannot be connected to an IC outside the chip for data communication use. 1. Features Features of SCI1 are listed below. * Choice of 8-bit or 16-bit transfer data length * Choice of 8 internal clocks (o/1024, o/256, o/64, o/32, o/16, o/8, o/4, or oW /4) as clock source * Interrupt request generated on completion of transfer 242 2. Block Diagram Figure 10-1 shows a block diagram of SCI1. o oW/4 PSS Transmit/receive control circuit SCSR1 Transfer bit counter SI1 SDRU SDRL SO1 IRRS1 Notation: SCR1: SCSR1: SDRU: SDRL: IRRS1: PSS: Serial control register 1 Serial control status register 1 Serial data register U Serial data register L Serial 1 interrupt request flag Prescaler S Figure 10-1 SCI1 Block Diagram Transfer bit counter SCK1 SCR1 243 3. I/O configuration Table 10-2 shows the SCI1 I/O configuration. Table 10-2 SCI1 I/O Configuration Name SCI1 clock SCI1 data input SCI1 data output Abbrev. SCK 1 SI 1 SO1 I/O I/O Input Output Function SCI1 clock input/output SCI1 receive data input SCI1 transmit data output 4. Register configuration Table 10-3 shows the SCI1 register configuration. Table 10-3 Registers Name Serial control register 1 Serial control status register 1 Serial data register U Serial data register L Clock stop register 1 Abbrev. SCR1 SCSR1 SDRU SDRL CKSTPR1 R/W R/W R/W R/W R/W R/W Initial Value H'00 H'9C Undefined Undefined H'FF Address H'FFA0 H'FFA1 H'FFA2 H'FFA3 H'FFFA 10.2.2 Register Descriptions 1. Serial control register 1 (SCR1) Bit Initial value Read/Write 7 SNC1 0 R/W 6 SNC0 0 R/W 5 MRKON 0 R/W 4 LTCH 0 R/W 3 CKS3 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SCR1 is an 8-bit read/write register that controls the operating mode, serial clock source, and prescaler division ratio. Upon reset, SCR1 is initialized to H'00. If this register is written to during transfer, transfer will be halted. 244 Bits 7 and 6: Operating mode select 1 and 0 (SNC1, SNC0) Bits 7 and 6 select the operating mode. Bit 7 SNC1 0 0 1 1 Bit 6 SNC0 0 1 0 1 Description 8-bit synchronous mode 16-bit synchronous mode Continuous clock output mode* 1 Reserved* 2 (initial value) Notes: 1. Use SI1 and SO1 as ports. 2. Do not set bits SNC1 and SNC0 to 11. Bit 5: Tail mark control (MRKON) Bit 5 controls tail mark output after transfer of 8-bit or 16-bit data. Bit 5 MRKON 0 1 Note: * Description Tail mark is not output (synchronous mode) Tail mark is output (SSB mode)* SCI1 is an internal function that performs interfacing to the on-chip FLEXTM decoder. It cannot be used with SSB mode selected. (initial value) Bit 4: LATCH TAIL select (LTCH) Bit 4 selects whether LATCH TAIL or HOLD TAIL is output as the tail mark when MRKON = 1 (i.e. in SSB mode). Bit 4 LTCH 0 1 Description HOLD TAIL is output LATCH TAIL is output (initial value) 245 Bit 3: Clock source select 3 (CKS3) Bit 3 selects the clock source to be supplied and sets the SCK1 to input or output mode. Bit 3 CKS3 0 1 Note: * Description Clock source is prescaler S, SCK 1 is output Clock source is external clock, SCK1 is input* SCI1 is an internal function that performs interfacing to the on-chip FLEXTM decoder. It cannot be used with SCK1 input selected. (initial value) Bits 2 to 0: Clock select 2 to 0 (CKS2 to CKS0) When CKS3 is cleared to 0, bits 2 to 0 selects the prescaler division ratio and the serial clock cycle. Bit 2 CKS2 0 0 0 0 1 1 1 1 Bit 1 CKS1 0 0 1 1 0 0 1 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 Serial Clock Cycle Prescaler Division Ratio o/1024 (initial value) o/256 o/64 o/32 o/16 o/8 o/4 oW/4 o = 2.5 MHz 409.6 s 102.4 s 25.6 s 12.8 s 6.4 s 3.2 s 1.6 s 50 s or 104.2 s 2. Serial control status register 1 (SCSR1) Bit Initial value Read/Write 7 -- 1 -- 6 SOL 0 R/W 5 ORER 0 R/(W)* 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 MTRF 0 R 0 STF 0 R/W Note: * Only a write of 0 for flag clearing is possible. SCSR1 is an 8-bit register that indicates the operational and error status of SCI1. Upon reset, SCSR1 is initialized to H'9C. 246 Bit 7: Reserved bit Bits 7 is reserved; it is always read as 1 and cannot be modified. Bit 6: Extension data bit (SOL) The SOL bit changes the output level of the SO1. When read, SOL returns the output level of the SO1. After transfer is completed, SO1 output retains the value of the last bit of the transmit data, and therefore the SO1 output level can be changed by manipulating this bit before or after transmission. However, the SOL bit setting becomes invalid when the next transmission starts*. Therefore, when changing the SO1 output level after transmission, a write operation must be performed on the SOL bit each time transmission is completed. Writing to this register during data transfer will cause incorrect operation, so this register should not be manipulated during transmission. Note: * The SOL bit setting is also invalid in SSB mode. Bit 6 SOL 0 Description Read Write 1 Read Write SO1 output level is low Changes SO 1 output to low level SO1 output level is high Changes SO 1 output to high level (initial value) Bit 5: Overrun error flag (ORER) Bit 5 indicates that an overrun error has occurred when using an external clock. If extra pulses are superimposed on the regular serial clock due to extraneous noise, etc., the transfer data cannot be guaranteed. If the clock is input after transfer is completed, this will be interpreted as an overrun state and this bit will be set to 1. Bit 5 ORER 0 1 Description Clearing conditions: After reading ORER = 1, cleared by writing 0 to ORER (initial value) Setting conditions: When an external clock is used and the clock is input after transfer is completed Bits 4 to 2: Reserved bits Bits 4 to 2 are reserved; they are always read as 1 and cannot be modified. 247 Bit 1: Tail mark transmission flag (MTRF) When MRKON = 1, bit 1 indicates that a tail mark is being transmitted. MTRF is a read-only bit, and cannot be modified. Bit 1 MTRF 0 1 Description Idle state, or 8-bit/16-bit data transfer in progress Tail mark transmission in progress (initial value) Bit 0: Start flag (STF) The STF bit controls the start of transfer operations. SCI1 transfer operation is started when this bit is set to 1. STF remains set to 1 during transfer and while SCI1 is waiting for a start bit, and is cleared to 0 when transfer ends. Bit 0 STF 0 Description Read Write 1 Read Write Transfer operation stopped Invalid Transfer operation in progress Starts transfer operation (initial value) 3. Serial data register U (SDRU) Bit Initial value Read/Write 7 SDRU7 R/W 6 5 4 3 2 SDRU2 R/W 1 0 SDRU6 SDRU5 R/W R/W SDRU4 SDRU3 R/W R/W SDRU1 SDRU0 R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined SDRU is an 8-bit read/write register used as the data register for the upper 8 bits in 16-bit transfer (while SDRL is used for the lower 8 bits). The data written into SDRU is output to SDRL in LSB-first order. In the replacement process, data is input LSB-first from the SI1 pin, and the data is shifted in the MSB LSB direction. SDRU read/write operations must only be performed after data transmission/reception has been completed. Data contents are not guaranteed if read/write operations are executed while data transmission/reception is in progress. The value of SDRU is undefined upon reset. 248 4. Serial data register L (SDRL) Bit Initial value Read/Write 7 SDRL7 R/W 6 SDRL6 R/W 5 SDRL5 R/W 4 SDRL4 R/W 3 SDRL3 R/W 2 SDRL2 R/W 1 SDRL1 R/W 0 SDRL0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined SDRL is an 8-bit read/write register used as the data register in 8-bit transfer, and as the data register for the lower 8 bits in 16-bit transfer (while SDRU is used for the upper 8 bits). In 8-bit transfer, the data written into SDRL is output from the SO1 in LSB-first order. In the replacement process, data is input LSB-first from the SI 1, and the data is shifted in the MSB LSB direction. The operation in 16-bit transfer is the same as for 8-bit transfer, except that the input data is taken from SDRU. SDRL read/write operations must only be performed after data transmission/reception has been completed. Data contents are not guaranteed if read/write operations are executed while data transmission/reception is in progress. The value of SDRL is undefined upon reset. 5. Clock stop register 1 (CKSTPR1) Bit 7 6 5 4 3 2 1 0 S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value Read/Write 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to SCI1 is described here. For details of the other bits, see the sections on the relevant modules. 249 Bit 7: SCI1 module standby mode control (S1CKSTP) Bit 7 controls setting and clearing of module standby mode for SCI1. Bit 7 S1CKSTP 0 1 Note: * Description SCI1 is set to module standby mode* 1 SCI1 module standby mode is cleared Setting to module standby mode resets SCR1, SCSR1, SDRU and SDRL. (initial value) 10.2.3 Operation Either 8-bit or 16-bit transfer data can be selected as the transfer format. Eight internal clocks can be selected as the clock source. 1. Clock The serial clock can be selected from 8 internal clocks. When an internal clock is selected, the SCK1 functions as the clock output. When continuous clock output mode is set (SNC1, SNC0 = 10 in SCR1), the clock selected by bits CKS2 to CKS0 (o/1024 to o W /4) is output continuously from the SCK1. 2. Data transfer format The SCI1 transfer format is shown in figure 10-2. LSB-first transfer is used (i.e. transmission and reception are performed starting with the least significant bit of the transfer data). Transfer data is output from one falling edge of the serial clock until the next falling edge. Receive data is latched at the rising edge of the serial clock. SCK1 SO1/SI1 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 10-2 Transfer Format 250 3. Data transfer operations Transmitting: The procedure for transmitting data is as follows. (1) Set both SO1 and SCK1 to 1 in PMR2 to designate the SO1 and SCK1 functions. (2) Clear SNC1 in SCR1 to 0, clear or set SNC0 to 0 or 1, and clear MRKON to 0, to select 8-bit synchronous mode or 16-bit synchronous mode, and select the serial clock with bits CKS3 to CKS0. When data is written to SCR1 with MRKON in SCR1 cleared to 0, the internal state of SCI1 is initialized. (3) Write the transfer data to SDRL/SDRU. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte to SDRU, lower byte to SDRL (4) When STF is set to 1 in SCSR1, SCI1 starts operating and transmit data is output from the SO1. (5) After transmission is completed, IRRS1 is set to 1 in IRR1. When an internal clock is used, the serial clock is output from the SCK1 simultaneously with transmit data output. When transmission ends, the serial clock is not output until the start flag is next set to 1. During this interval, the SO1 continuously outputs the last bit of the previous data. While transmission is halted, the output value of the SO1 can be changed by means of the SOL bit in SCSR1. Receiving: The procedure for receiving data is as follows. (1) Set both SI1 and SCK1 to 1 in PMR2 to designate the SI1 and SCK1 functions. (2) Clear SNC1 in SCR1 to 0, clear or set SNC0 to 0 or 1, and clear MRKON to 0, to select 8-bit synchronous mode or 16-bit synchronous mode, and select the serial clock with bits CKS3 to CKS0. When data is written to SCR1 with MRKON in SCR1 cleared to 0, the internal state of SCI1 is initialized. (3) When STF is set to 1 in SCSR1, SCI1 starts operating and receive data is taken in from the SI1. (4) After reception is completed, IRRS1 is set to 1 in IRR1. (5) Read the transfer data from SDRL/SDRU. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte from SDRU, lower byte from SDRL 251 Simultaneous transmitting and receiving: The procedure for simultaneously transmitting and receiving data is as follows. (1) Set SO1, SI1, and SCK1 all to 1 in PMR2 to designate the SO1, SI1, and SCK1 functions. (2) Clear SNC1 in SCR1 to 0, clear or set SNC0 to 0 or 1, and clear MRKON to 0, to select 8-bit synchronous mode or 16-bit synchronous mode, and select the serial clock with bits CKS3 to CKS0. When data is written to SCR1 with MRKON in SCR1 cleared to 0, the internal state of SCI1 is initialized. (3) Write the transfer data to SDRL/SDRU. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte to SDRU, lower byte to SDRL (4) When STF is set to 1 in SCSR1, SCI1 starts operating and transmit data is output from the SO1, or receive data is input from the SI1. (5) After transmission/reception is completed, IRRS1 is set to 1 in IRR1. (6) Read the transfer data from SDRL/SDRU. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte from SDRU, lower byte from SDRL When an internal clock is used, the serial clock is output from the SCK1 simultaneously with transmit data output. When transmission ends, the serial clock is not output until the start flag is next set to 1. During this interval, the SO1 continuously outputs the last bit of the previous data. While transmission is halted, the output value of the SO1 pin can be changed by means of the SOL bit in SCSR1. 10.2.4 Interrupt Source SCI1 has one interrupt source: transfer completion. When SCI1 completes transfer, IRRS1 is set to 1 in IRR1. The SCI1 interrupt source can be enabled or disabled by the IENS1 bit in IENR1. For details, see 3.3, Interrupts. 252 10.2.5 Application Note (1) Conditions for use of SCI1 in subactive mode and subsleep mode In subactive or subsleep mode, SCI1 can be used only when the CPU operation clock is oW /2. (2) Confirming the end of serial transfer Do not read or write to SCSR1 during serial transfer. The following two methods can be used to confirm the end of serial transfer: (a) Using SCI1 interrupt exception handling Set the IENS1 bit to 1 in IENR1 and execute interrupt exception handling. (b) Performing IRR1 polling With SCI1 interrupts disabled (IENS1 = 0 in IENR1), confirm that the IRRS1 bit in IRR1 has been set to 1. 253 10.3 10.3.1 SCI3 Overview In addition to SCI1, the H8/3937 Series and H8/3937R Series have two serial communication interfaces, SCI31 and SCI32, with identical functions. In this manual, the generic term SCI3 is used to refer to both of these SCIs. Serial communication interface 3 (SCI3) can carry out serial data communication in either asynchronous or synchronous mode. It is also provided with a multiprocessor communication function that enables serial data to be transferred among processors. 1. Features Features of SCI3 are listed below. * Choice of asynchronous or synchronous mode for serial data communication Asynchronous mode Serial data communication is performed asynchronously, with synchronization provided character by character. In this mode, serial data can be exchanged with standard asynchronous communication LSIs such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A multiprocessor communication function is also provided, enabling serial data communication among processors. There is a choice of 16 data transfer formats. Data length Stop bit length Parity Multiprocessor bit Receive error detection Break detection 7, 8, 5 bits 1 or 2 bits Even, odd, or none 1 or 0 Parity, overrun, and framing errors Break detected by reading the RXD 3X pin level directly when a framing error occurs 254 Synchronous mode Serial data communication is synchronized with a clock. In his mode, serial data can be exchanged with another LSI that has a synchronous communication function. Data length Receive error detection 8 bits Overrun errors * Full-duplex communication Separate transmission and reception units are provided, enabling transmission and reception to be carried out simultaneously. The transmission and reception units are both double-buffered, allowing continuous transmission and reception. * On-chip baud rate generator, allowing any desired bit rate to be selected * Choice of an internal or external clock as the transmit/receive clock source * Six interrupt sources: transmit end, transmit data empty, receive data full, overrun error, framing error, and parity error 255 2. Block diagram Figure 10-3 shows a block diagram of SCI3. SCK 3x External clock Internal clock (o/64, o/16, ow/2, o) Baud rate generator BRC Clock BRR Transmit/receive control circuit SCR3 SSR TXD SPCR RXD TSR TDR RSR RDR Interrupt request (TEI, TXI, RXI, ERI) Notation: RSR: RDR: TSR: TDR: SMR: SCR3: SSR: BRR: BRC: SPCR: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register 3 Serial status register Bit rate register Bit rate counter Serial port control register Figure 10-3 SCI3 Block Diagram 256 Internal data bus SMR 3. Pin configuration Table 10-4 shows the SCI3 pin configuration. Table 10-4 Pin Configuration Name SCI3 clock SCI3 receive data input SCI3 transmit data output Abbrev. SCK 3X RXD3X TXD3X I/O I/O Input Output Function SCI3 clock input/output SCI3 receive data input SCI3 transmit data output 4. Register configuration Table 10-5 shows the SCI3 register configuration. Table 10-5 Registers Name Serial mode register Bit rate register Serial control register 3 Transmit data register Serial data register Receive data register Transmit shift register Receive shift register Bit rate counter Clock stop register 1 Serial port control register Abbrev. SMR BRR SCR3 TDR SSR RDR TSR RSR BRC CKSTPR1 SPCR R/W R/W R/W R/W R/W R/W R Protected Protected Protected R/W R/W Initial Value H'00 H'FF H'00 H'FF H'84 H'00 -- -- -- H'FF H'C0 Address H'FFA8/FF98 H'FFA9/FF99 H'FFAA/FF9A H'FFAB/FF9B H'FFAC/FF9C H'FFAD/FF9D -- -- -- H'FFFA H'FF91 257 10.3.2 Register Descriptions 1. Receive shift register (RSR) Bit 7 6 5 4 3 2 1 0 Read/Write -- -- -- -- -- -- -- -- RSR is a register used to receive serial data. Serial data input to RSR from the RXD3X pin is set in the order in which it is received, starting from the LSB (bit 0), and converted to parallel data. When one byte of data is received, it is transferred to RDR automatically. RSR cannot be read or written directly by the CPU. 2. Receive data register (RDR) Bit Initial value Read/Write 7 RDR7 0 R 6 RDR6 0 R 5 RDR5 0 R 4 RDR4 0 R 3 RDR3 0 R 2 RDR2 0 R 1 RDR1 0 R 0 RDR0 0 R RDR is an 8-bit register that stores received serial data. When reception of one byte of data is finished, the received data is transferred from RSR to RDR, and the receive operation is completed. RSR is then able to receive data. RSR and RDR are double-buffered, allowing consecutive receive operations. RDR is a read-only register, and cannot be written by the CPU. RDR is initialized to H'00 upon reset, and in standby, watch or module standby mode. 258 3. Transmit shift register (TSR) Bit 7 6 5 4 3 2 1 0 Read/Write -- -- -- -- -- -- -- -- TSR is a register used to transmit serial data. Transmit data is first transferred from TDR to TSR, and serial data transmission is carried out by sending the data to the TXD 3X pin in order, starting from the LSB (bit 0). When one byte of data is transmitted, the next byte of transmit data is transferred to TDR, and transmission started, automatically. Data transfer from TDR to TSR is not performed if no data has been written to TDR (if bit TDRE is set to 1 in the serial status register (SSR)). TSR cannot be read or written directly by the CPU. 4. Transmit data register (TDR) Bit Initial value Read/Write 7 TDR7 1 R/W 6 TDR6 1 R/W 5 TDR5 1 R/W 4 TDR4 1 R/W 3 TDR3 1 R/W 2 TDR2 1 R/W 1 TDR1 1 R/W 0 TDR0 1 R/W TDR is an 8-bit register that stores transmit data. When TSR is found to be empty, the transmit data written in TDR is transferred to TSR, and serial data transmission is started. Continuous transmission is possible by writing the next transmit data to TDR during TSR serial data transmission. TDR can be read or written by the CPU at any time. TDR is initialized to H'FF upon reset, and in standby, watch or module standby mode. 259 5. Serial mode register (SMR) Bit Initial value Read/Write 7 COM 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 PM 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for the baud rate generator. SMR can be read or written by the CPU at any time. SMR is initialized to H'00 upon reset, and in standby, watch or module standby mode. Bit 7: Communication mode (COM) Bit 7 selects whether SCI3 operates in asynchronous mode or synchronous mode. Bit 7 COM 0 1 Description Asynchronous mode Synchronous mode (initial value) Bit 6: Character length (CHR) Bit 6 selects either 7 or 8 bits as the data length to be used in asynchronous mode. In synchronous mode the data length is always 8 bits, irrespective of the bit 6 setting. Bit 6 CHR 0 1 Description 8-bit data/5-bit data* 2 7-bit data* /5-bit data* 1 2 (initial value) Notes: 1. When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. 2. When 5-bit data is selected, set both PE and MP to 1. The three most significant bits (bits 7, 6, and 5) of TDR are not transmitted. 260 Bit 5: Parity enable (PE) Bit 5 selects whether a parity bit is to be added during transmission and checked during reception in asynchronous mode. In synchronous mode parity bit addition and checking is not performed, irrespective of the bit 5 setting. Bit 5 PE 0 1 Description Parity bit addition and checking disabled* 2 Parity bit addition and checking enabled* * 1/ 2 (initial value) Notes: 1. When PE is set to 1, even or odd parity, as designated by bit PM, is added to transmit data before it is sent, and the received parity bit is checked against the parity designated by bit PM. 2. For the case where 5-bit data is selected, see table 10-11. Bit 4: Parity mode (PM) Bit 4 selects whether even or odd parity is to be used for parity addition and checking. The PM bit setting is only valid in asynchronous mode when bit PE is set to 1, enabling parity bit addition and checking. The PM bit setting is invalid in synchronous mode, and in asynchronous mode if parity bit addition and checking is disabled. Bit 4 PM 0 1 Description Even parity* 1 Odd parity* 2 (initial value) Notes: 1. When even parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an even number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an even number. 2. When odd parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an odd number. 261 Bit 3: Stop bit length (STOP) Bit 3 selects 1 bit or 2 bits as the stop bit length is asynchronous mode. The STOP bit setting is only valid in asynchronous mode. When synchronous mode is selected the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP 0 1 Description 1 stop bit* 1 2 stop bits* 2 (initial value) Notes: 1. In transmission, a single 1 bit (stop bit) is added at the end of a transmit character. 2. In transmission, two 1 bits (stop bits) are added at the end of a transmit character. In reception, only the first of the received stop bits is checked, irrespective of the STOP bit setting. If the second stop bit is 1 it is treated as a stop bit, but if 0, it is treated as the start bit of the next transmit character. Bit 2: Multiprocessor mode (MP) Bit 2 enables or disables the multiprocessor communication function. When the multiprocessor communication function is disabled, the parity settings in the PE and PM bits are invalid. The MP bit setting is only valid in asynchronous mode. When synchronous mode is selected the MP bit should be set to 0. For details on the multiprocessor communication function, see 10.1.6, Multiprocessor Communication Function. Bit 2 MP 0 1 Note: * Description Multiprocessor communication function disabled* Multiprocessor communication function enabled* For the case where 5-bit data is selected, see table 10-11. (initial value) 262 Bits 1 and 0: Clock select 1 and 0 (CKS1, CKS0) Bits 1 and 0 choose o/64, o/16, o/2, or o as the clock source for the baud rate generator. For the relation between the clock source, bit rate register setting, and baud rate, see 8, Bit rate register (BRR). Bit 1 CKS1 0 0 1 1 Bit 0 CKS0 0 1 0 1 Description o clock oW/2 clock* /oW clock* o/16 clock o/64 clock 1 2 (initial value) Notes: 1. oW/2 clock is selected in active (medium- and high-speed) or sleep (medium- and highspeed) mode. 2. oW clock is selected in subactive or subsleep mode. SCI3 can be used only when the oW/2 is selected as the CPU clock in subactive or subsleep mode. 6. Serial control register 3 (SCR3) Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W SCR3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock output, interrupt request enabling or disabling, and the transmit/receive clock source. SCR3 can be read or written by the CPU at any time. SCR3 is initialized to H'00 upon reset, and in standby, watch or module standby mode. 263 Bit 7: Transmit interrupt enable (TIE) Bit 7 selects enabling or disabling of the transmit data empty interrupt request (TXI) when transmit data is transferred from the transmit data register (TDR) to the transmit shift register (TSR), and bit TDRE in the serial status register (SSR) is set to 1. TXI can be released by clearing bit TDRE or bit TIE to 0. Bit 7 TIE 0 1 Description Transmit data empty interrupt request (TXI) disabled Transmit data empty interrupt request (TXI) enabled (initial value) Bit 6: Receive interrupt enable (RIE) Bit 6 selects enabling or disabling of the receive data full interrupt request (RXI) and the receive error interrupt request (ERI) when receive data is transferred from the receive shift register (RSR) to the receive data register (RDR), and bit RDRF in the serial status register (SSR) is set to 1. There are three kinds of receive error: overrun, framing, and parity. RXI can be released by clearing bit RDRF or the FER, PER, or OER error flag to 0, or by clearing bit RIE to 0. Bit 6 RIE 0 1 Description Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled (initial value) Bit 5: Transmit enable (TE) Bit 5 selects enabling or disabling of the start of transmit operation. Bit 5 TE 0 1 Description Transmit operation disabled* 1 (TXD pin is I/O port) Transmit operation enabled* (TXD pin is transmit data pin) 2 (initial value) Notes: 1. Bit TDRE in SSR is fixed at 1. 2. When transmit data is written to TDR in this state, bit TDR in SSR is cleared to 0 and serial data transmission is started. Be sure to carry out serial mode register (SMR) settings, and setting of bit SPC31 or SPC32 in SPCR, to decide the transmission format before setting bit TE to 1. 264 Bit 4: Receive enable (RE) Bit 4 selects enabling or disabling of the start of receive operation. Bit 4 RE 0 1 Description Receive operation disabled* 1 (RXD pin is I/O port) Receive operation enabled* (RXD pin is receive data pin) 2 (initial value) Notes: 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is cleared to 0, and retain their previous state. 2. In this state, serial data reception is started when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. Be sure to carry out serial mode register (SMR) settings to decide the reception format before setting bit RE to 1. Bit 3: Multiprocessor interrupt enable (MPIE) Bit 3 selects enabling or disabling of the multiprocessor interrupt request. The MPIE bit setting is only valid when asynchronous mode is selected and reception is carried out with bit MP in SMR set to 1. The MPIE bit setting is invalid when bit COM is set to 1 or bit MP is cleared to 0. Bit 3 MPIE 0 Description Multiprocessor interrupt request disabled (normal receive operation) Clearing conditions: When data is received in which the multiprocessor bit is set to 1 Multiprocessor interrupt request enabled* * Receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and OER status flags in SSR is not performed. RXI, ERI, and setting of the RDRF, FER, and OER flags in SSR, are disabled until data with the multiprocessor bit set to 1 is received. When a receive character with the multiprocessor bit set to 1 is received, bit MPBR in SSR is set to 1, bit MPIE is automatically cleared to 0, and RXI and ERI requests (when bits TIE and RIE in serial control register 3 (SCR3) are set to 1) and setting of the RDRF, FER, and OER flags are enabled. (initial value) 1 Note: 265 Bit 2: Transmit end interrupt enable (TEIE) Bit 2 selects enabling or disabling of the transmit end interrupt request (TEI) if there is no valid transmit data in TDR when MSB data is to be sent. Bit 2 TEIE 0 1 Note: * Description Transmit end interrupt request (TEI) disabled Transmit end interrupt request (TEI) enabled* TEI can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by clearing bit TEIE to 0. (initial value) Bits 1 and 0: Clock enable 1 and 0 (CKE1, CKE0) Bits 1 and 0 select the clock source and enabling or disabling of clock output from the SCK3X pin. The combination of CKE1 and CKE0 determines whether the SCK 3X pin functions as an I/O port, a clock output pin, or a clock input pin. The CKE0 bit setting is only valid in case of internal clock operation (CKE1 = 0) in asynchronous mode. In synchronous mode, or when external clock operation is used (CKE1 = 1), bit CKE0 should be cleared to 0. After setting bits CKE1 and CKE0, set the operating mode in the serial mode register (SMR). For details on clock source selection, see table 10-4 in 10.1.3, Operation. Bit 1 CKE1 0 Bit 0 CKE0 0 Description Communication Mode Asynchronous Synchronous 0 1 Asynchronous Synchronous 1 0 Asynchronous Synchronous 1 1 Asynchronous Synchronous Clock Source Internal clock Internal clock Internal clock Reserved External clock External clock Reserved Reserved Clock input* 3 Serial clock input SCK3X Pin Function I/O port* 1 Serial clock output* 1 Clock output* 2 Notes: 1. Initial value 2. A clock with the same frequency as the bit rate is output. 3. Input a clock with a frequency 16 times the bit rate. 266 7. Serial status register (SSR) Bit Initial value Read/Write Note: * 7 TDRE 1 R/(W) * 6 RDRF 0 R/(W)* 5 OER 0 R/(W) * 4 FER 0 R/(W)* 3 PER 0 R/(W) * 2 TEND 1 R 1 MPBR 0 R 0 MPBT 0 R/W Only a write of 0 for flag clearing is possible. SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and multiprocessor bits. SSR can be read or written by the CPU at any time, but only a write of 1 is possible to bits TDRE, RDRF, OER, PER, and FER. In order to clear these bits by writing 0, 1 must first be read. Bits TEND and MPBR are read-only bits, and cannot be modified. SSR is initialized to H'84 upon reset, and in standby, module standby, or watch mode. Bit 7: Transmit data register empty (TDRE) Bit 7 indicates that transmit data has been transferred from TDR to TSR. Bit 7 TDRE 0 Description Transmit data written in TDR has not been transferred to TSR Clearing conditions: After reading TDRE = 1, cleared by writing 0 to TDRE When data is written to TDR by an instruction Transmit data has not been written to TDR, or transmit data written in TDR has been transferred to TSR Setting conditions: When bit TE in SCR3 is cleared to 0 When data is transferred from TDR to TSR (initial value) 1 267 Bit 6: Receive data register full (RDRF) Bit 6 indicates that received data is stored in RDR. Bit 6 RDRF 0 Description There is no receive data in RDR Clearing conditions: After reading RDRF = 1, cleared by writing 0 to RDRF When RDR data is read by an instruction (initial value) 1 There is receive data in RDR Setting conditions: When reception ends normally and receive data is transferred from RSR to RDR Note: If an error is detected in the receive data, or if the RE bit in SCR3 has been cleared to 0, RDR and bit RDRF are not affected and retain their previous state. Note that if data reception is completed while bit RDRF is still set to 1, an overrun error (OER) will result and the receive data will be lost. Bit 5: Overrun error (OER) Bit 5 indicates that an overrun error has occurred during reception. Bit 5 OER 0 Description Reception in progress or completed* 1 Clearing conditions: After reading OER = 1, cleared by writing 0 to OER An overrun error has occurred during reception* 2 Setting conditions: When reception is completed with RDRF set to 1 (initial value) 1 Notes: 1. When bit RE in SCR3 is cleared to 0, bit OER is not affected and retains its previous state. 2. RDR retains the receive data it held before the overrun error occurred, and data received after the error is lost. Reception cannot be continued with bit OER set to 1, and in synchronous mode, transmission cannot be continued either. 268 Bit 4: Framing error (FER) Bit 4 indicates that a framing error has occurred during reception in asynchronous mode. Bit 4 FER 0 Description Reception in progress or completed* 1 Clearing conditions: After reading FER = 1, cleared by writing 0 to FER A framing error has occurred during reception Setting conditions: When the stop bit at the end of the receive data is checked for a value of 1 at the end of reception, and the stop bit is 0* 2 (initial value) 1 Notes: 1. When bit RE in SCR3 is cleared to 0, bit FER is not affected and retains its previous state. 2. Note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the second stop bit is not checked. When a framing error occurs the receive data is transferred to RDR but bit RDRF is not set. Reception cannot be continued with bit FER set to 1. In synchronous mode, neither transmission nor reception is possible when bit FER is set to 1. Bit 3: Parity error (PER) Bit 3 indicates that a parity error has occurred during reception with parity added in asynchronous mode. Bit 3 PER 0 Description Reception in progress or completed* 1 Clearing conditions: After reading PER = 1, cleared by writing 0 to PER A parity error has occurred during reception* 2 Setting conditions: When the number of 1 bits in the receive data plus parity bit does not match the parity designated by bit PM in the serial mode register (SMR) (initial value) 1 Notes: 1. When bit RE in SCR3 is cleared to 0, bit PER is not affected and retains its previous state. 2. Receive data in which it a parity error has occurred is still transferred to RDR, but bit RDRF is not set. Reception cannot be continued with bit PER set to 1. In synchronous mode, neither transmission nor reception is possible when bit FER is set to 1. 269 Bit 2: Transmit end (TEND) Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent. Bit 2 is a read-only bit and cannot be modified. Bit 2 TEND 0 Description Transmission in progress Clearing conditions: After reading TDRE = 1, cleared by writing 0 to TDRE When data is written to TDR by an instruction Transmission ended Setting conditions: When bit TE in SCR3 is cleared to 0 When bit TDRE is set to 1 when the last bit of a transmit character is sent (initial value) 1 Bit 1: Multiprocessor bit receive (MPBR) Bit 1 stores the multiprocessor bit in a receive character during multiprocessor format reception in asynchronous mode. Bit 1 is a read-only bit and cannot be modified. Bit 1 MPBR 0 1 Note: * Description Data in which the multiprocessor bit is 0 has been received* Data in which the multiprocessor bit is 1 has been received When bit RE is cleared to 0 in SCR3 with the multiprocessor format, bit MPBR is not affected and retains its previous state. (initial value) Bit 0: Multiprocessor bit transfer (MPBT) Bit 0 stores the multiprocessor bit added to transmit data when transmitting in asynchronous mode. The bit MPBT setting is invalid when synchronous mode is selected, when the multiprocessor communication function is disabled, and when not transmitting. Bit 0 MPBT 0 1 Description A 0 multiprocessor bit is transmitted A 1 multiprocessor bit is transmitted (initial value) 270 8. Bit rate register (BRR) Bit Initial value Read/Write 7 BRR7 1 R/W 6 BRR6 1 R/W 5 BRR5 1 R/W 4 BRR4 1 R/W 3 BRR3 1 R/W 2 BRR2 1 R/W 1 BRR1 1 R/W 0 BRR0 1 R/W BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR). BRR can be read or written by the CPU at any time. BRR is initialized to H'FF upon reset, and in standby, module standby, or watch mode. Table 10-6 shows examples of BRR settings in asynchronous mode. The values shown are for active (high-speed) mode. Table 10-6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) OSC 32.8 kHz Bit Rate (bit/s) n 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 N 38.4 kHz Error (%) n -- 0 0 -- 0 0 -- -- -- -- -- -- -- N -- 3 2 -- 1 0 -- -- -- -- -- -- -- 2 MHz Error (%) n -- 0 0 -- 0 0 -- -- -- -- -- -- -- -- 2 0 0 0 0 0 0 -- -- -- 0 -- N -- 12 155 124 103 51 25 12 -- -- -- 0 -- 2.4576 MHz Error (%) n -- 0.16 0.16 0 0.16 0.16 0.16 0.16 -- -- -- 0 -- 2 3 3 0 3 3 2 2 0 0 0 -- 0 N 21 3 2 153 1 0 1 0 7 3 1 -- 0 4 MHz Error (%) n -0.83 -- 0 0 2 -- N -- 25 -- 249 12 103 51 25 12 -- -- 1 -- Error (%) -- 0.16 -- 0 0.16 0.16 0.16 0.16 0.16 -- -- 0 -- Cannot be used, as error exceeds 3% -0.26 0 0 0 0 0 0 0 0 -- 0 2 0 0 0 0 -- -- 0 -- 271 Table 10-6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) OSC 10 MHz Bit Rate (bit/s) n 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 2 2 2 2 -- -- 0 0 -- -- -- 0 -- N 88 64 48 38 -- -- 129 64 -- -- -- 4 -- 16 MHz Error (%) n -0.25 2 0.16 2 N 141 103 77 62 51 25 207 103 51 25 12 7 -- Error (%) -0.02 0.16 0.16 -0.79 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 -- -0.35 2 0.16 -- -- 0.16 0.16 -- -- -- 0 -- 2 2 2 0 0 0 0 0 0 -- Notes: 1. The setting should be made so that the error is not more than 1%. 2. The value set in BRR is given by the following equation: OSC N= --1 (64 x 2 2n x B) where B: Bit rate (bit/s) N: Baud rate generator BRR setting (0 N 255) OSC: Value of o OSC (Hz) n: Baud rate generator input clock number (n = 0, 2, or 3) (The relation between n and the clock is shown in table 10-7.) 3. The error in table 10-6 is the value obtained from the following equation, rounded to two decimal places. Error (%) = B (rate obtained from n, N, OSC) -- R (bit rate in left-hand column in table 10-6.) R (bit rate in left-hand column in table 10-6.) x 100 272 Table 10-7 Relation between n and Clock SMR Setting n 0 0 2 3 Clock o oW/2* /oW * o/16 o/64 1 2 CKS1 0 0 1 1 CKS0 0 1 0 1 Notes: 1. oW/2 clock is selected in active (medium- and high-speed) or sleep (medium- and highspeed) mode. 2. oW clock is selected in subactive or subsleep mode. SCI3 can be used only when the oW/2 is selected as the CPU clock in subactive or subsleep mode. Table 10-8 shows the maximum bit rate for each frequency. The values shown are for active (high-speed) mode. Table 10-8 Maximum Bit Rate for Each Frequency (Asynchronous Mode) Setting OSC (MHz) 0.0384* 2 2.4576 4 10 16 Note: * Maximum Bit Rate (bit/s) 600 31250 38400 62500 156250 250000 When SMR is set up to CKS1 = 0, CKS0 = 1. n 0 0 0 0 0 0 N 0 0 0 0 0 0 Table 10-9 shows examples of BRR settings in synchronous mode. The values shown are for active (high-speed) mode. 273 Table 10-9 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (1) OSC 38.4 kHz Bit Rate (bit/s) n 200 250 300 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 0 -- 2 N 23 -- 0 Error 0 -- 0 -- 0 0 0 0 0 0 -- 0 2 MHz n -- -- -- -- 249 99 49 24 9 4 -- 0 N -- -- -- -- 0 0 0 0 0 0 -- 0 Error -- -- -- -- -- 0 0 0 0 0 0 0 0 4 MHz n -- 2 -- -- -- 199 99 49 19 9 4 1 0 N -- 124 -- -- -- 0 0 0 0 0 0 0 0 Error -- 0 -- 274 Table 10-9 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (2) OSC 10 MHz Bit Rate (bit/s) n 200 250 300 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M -- -- -- -- -- -- 0 0 0 0 -- 0 -- -- N -- -- -- -- -- -- 249 124 49 24 -- 4 -- -- Error -- -- -- -- -- -- 0 0 0 0 -- 0 -- -- 16 MHz n -- 3 -- 2 2 2 2 0 0 0 0 0 0 0 N -- 124 -- 249 124 49 24 199 79 39 19 7 3 1 Error -- 0 -- 0 0 0 0 0 0 0 0 0 0 0 Blank: Cannot be set. -- : A setting can be made, but an error will result. * : Continuous transmission/reception is not possible. Notes: The value set in BRR is given by the following equation: OSC N= --1 (8 x 2 2n x B) where B: Bit rate (bit/s) N: Baud rate generator BRR setting (0 N 255) OSC: Value of o OSC (Hz) n: Baud rate generator input clock number (n = 0, 2, or 3) (The relation between n and the clock is shown in table 10-10.) 275 Table 10-10 Relation between n and Clock SMR Setting n 0 0 2 3 Clock o oW/2* 1/oW * 2 o/16 o/64 CKS1 0 0 1 1 CKS0 0 1 0 1 Notes: 1. oW/2 clock is selected in active (medium- and high-speed) or sleep (medium- and highspeed) mode. 2. oW clock is selected in subactive or subsleep mode. SCI3 can be used only when the oW/2 is selected as the CPU operation clock in subactive or subsleep mode. 276 9. Clock stop register 1 (CKSTPR1) Bit 7 6 5 4 3 2 1 0 S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value Read/Write 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bits relating to SCI3 are described here. For details of the other bits, see the sections on the relevant modules. Bit 6: SCI31 module standby mode control (S31CKSTP) Bit 6 controls setting and clearing of module standby mode for SCI31. S31CKSTP 0 1 Note: * Description SCI31 is set to module standby mode* SCI31 module standby mode is cleared Setting to module standby mode resets all the registers in SCI31. (initial value) Bit 5: SCI32 module standby mode control (S32CKSTP) Bit 5 controls setting and clearing of module standby mode for SCI32. S32CKSTP 0 1 Note: * Description SCI32 is set to module standby mode* SCI32 module standby mode is cleared Setting to module standby mode resets all the registers in SCI32. (initial value) 277 10. Serial Port Control Register (SPCR) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 SPC32 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W SPC31 SCINV3 SCINV2 SCINV1 SCINV0 SPCR is an 8-bit readable/writable register that performs RXD31, RXD32, TXD31, and TXD32 pin input/output data inversion switching. SPCR is initialized to H'C0 by a reset. Bits 7 and 6: Reserved bits Bits 7 and 6 are reserved; they are always read as 1 and cannot be modified. Bit 5: P42/TXD32 pin function switch (SPC32) This bit selects whether pin P42/TXD32 is used as P42 or as TXD32. Bit 5 SPC32 0 1 Note: * Description Functions as P4 2 I/O pin Functions as TXD 32 output pin* Set the TE bit in SCR3 after setting this bit to 1. (initial value) Bit 4: P35/TXD31 pin function switch (SPC31) This bit selects whether pin P35/TXD31 is used as P35 or as TXD31. Bit 4 SPC31 0 1 Note: * Description Functions as P3 5 I/O pin Functions as TXD 31 output pin* Set the TE bit in SCR3 after setting this bit to 1. (initial value) Bit 3: TXD32 pin output data inversion switch Bit 3 specifies whether or not TXD32 pin output data is to be inverted. Bit 3 SCINV3 0 1 Description TXD32 output data is not inverted TXD32 output data is inverted (initial value) 278 Bit 2: RXD 32 pin input data inversion switch Bit 2 specifies whether or not RXD 32 pin input data is to be inverted. Bit 2 SCINV2 0 1 Description RXD32 input data is not inverted RXD32 input data is inverted (initial value) Bit 1: TXD31 pin output data inversion switch Bit 1 specifies whether or not TXD31 pin output data is to be inverted. Bit 1 SCINV1 0 1 Description TXD31 output data is not inverted TXD31 output data is inverted (initial value) Bit 0: RXD 31 pin input data inversion switch Bit 0 specifies whether or not RXD 31 pin input data is to be inverted. Bit 0 SCINV0 0 1 Description RXD31 input data is not inverted RXD31 input data is inverted (initial value) 279 10.3.3 Operation 1. Overview SCI3 can perform serial communication in two modes: asynchronous mode in which synchronization is provided character by character, and synchronous mode in which synchronization is provided by clock pulses. The serial mode register (SMR) is used to select asynchronous or synchronous mode and the data transfer format, as shown in table 10-11. The clock source for SCI3 is determined by bit COM in SMR and bits CKE1 and CKE0 in SCR3, as shown in table 10-12. a. Asynchronous mode * Choice of 5-, 7-, or 8-bit data length * Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits. (The combination of these parameters determines the data transfer format and the character length.) * Framing error (FER), parity error (PER), overrun error (OER), and break detection during reception * Choice of internal or external clock as the clock source When internal clock is selected: SCI3 operates on the baud rate generator clock, and a clock with the same frequency as the bit rate can be output. When external clock is selected: A clock with a frequency 16 times the bit rate must be input. (The on-chip baud rate generator is not used.) b. Synchronous mode * Data transfer format: Fixed 8-bit data length * Overrun error (OER) detection during reception * Choice of internal or external clock as the clock source When internal clock is selected: SCI3 operates on the baud rate generator clock, and a serial clock is output. When external clock is selected: The on-chip baud rate generator is not used, and SCI3 operates on the input serial clock. 280 Table 10-11 SMR Settings and Corresponding Data Transfer Formats SMR bit 7 COM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 bit 6 CHR 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 * bit 2 MP 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 bit 5 PE 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 * bit 3 STOP Mode 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * Synchronous mode 8-bit data No No 5-bit data No Yes 7-bit data Yes 5-bit data No 8-bit data Yes No Yes 7-bit data No Data Transfer Format Data Length Multiprocessor Parity Bit Bit No Stop Bit Length 1 bit 2 bits Yes 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits No *: Don't care Asynchronous 8-bit data No mode 281 Table 10-12 SMR and SCR3 Settings and Clock Source Selection SMR bit 7 COM 0 0 0 1 1 0 1 1 SCR3 bit 1 bit 0 Transmit/Receive Clock Clock Source SCK3X Pin Function I/O port (SCK3X pin not used) Outputs clock with same frequency as bit rate Outputs clock with frequency 16 times bit rate Outputs serial clock Inputs serial clock CKE1 CKE0 Mode 0 0 1 0 1 1 0 1 0 1 0 0 0 1 1 1 Synchronous mode Asynchronous Internal mode External Internal External Reserved (Do not specify these combinations) 282 c. Interrupts and continuous transmission/reception SCI3 can carry out continuous reception using RXI and continuous transmission using TXI. These interrupts are shown in table 10-13. Table 10-13 Transmit/Receive Interrupts Interrupt Flags RXI RDRF RIE Interrupt Request Conditions When serial reception is performed normally and receive data is transferred from RSR to RDR, bit RDRF is set to 1, and if bit RIE is set to 1 at this time, RXI is enabled and an interrupt is requested. (See figure 10-4 (a).) When TSR is found to be empty (on completion of the previous transmission) and the transmit data placed in TDR is transferred to TSR, bit TDRE is set to 1. If bit TIE is set to 1 at this time, TXI is enabled and an interrupt is requested. (See figure 10-4 (b).) When the last bit of the character in TSR is transmitted, if bit TDRE is set to 1, bit TEND is set to 1. If bit TEIE is set to 1 at this time, TEI is enabled and an interrupt is requested. (See figure 10-4 (c).) Notes The RXI interrupt routine reads the receive data transferred to RDR and clears bit RDRF to 0. Continuous reception can be performed by repeating the above operations until reception of the next RSR data is completed. The TXI interrupt routine writes the next transmit data to TDR and clears bit TDRE to 0. Continuous transmission can be performed by repeating the above operations until the data transferred to TSR has been transmitted. TEI indicates that the next transmit data has not been written to TDR when the last bit of the transmit character in TSR is sent. TXI TDRE TIE TEI TEND TEIE 283 RDR RDR RSR (reception in progress) RXD3x pin RDRF = 0 RXD3x pin RSR (reception completed, transfer) RDRF 1 (RXI request when RIE = 1) Figure 10-4 (a) RDRF Setting and RXI Interrupt TDR (next transmit data) TDR TSR (transmission in progress) TXD3x pin TDRE = 0 TXD3x pin TSR (transmission completed, transfer) TDRE 1 (TXI request when TIE = 1) Figure 10-4 (b) TDRE Setting and TXI Interrupt TDR TDR TSR (transmission in progress) TXD3x pin TEND = 0 TXD3x pin TSR (reception completed) TEND 1 (TEI request when TEIE = 1) Figure 10-4 (c) TEND Setting and TEI Interrupt 284 2. Operation in Asynchronous Mode In asynchronous mode, serial communication is performed with synchronization provided character by character. A start bit indicating the start of communication and one or two stop bits indicating the end of communication are added to each character before it is sent. SCI3 has separate transmission and reception units, allowing full-duplex communication. As the transmission and reception units are both double-buffered, data can be written during transmission and read during reception, making possible continuous transmission and reception. a. Data transfer format The general data transfer format in asynchronous communication is shown in figure 10-5. (LSB) Serial data Start bit Transmit/receive data (MSB) Parity bit Stop bit(s) 1 Mark state 1 bit 5, 7 or 8 bits 1 bit or none 1 or 2 bits One transfer data unit (character or frame) Figure 10-5 Data Format in Asynchronous Communication In asynchronous communication, the communication line is normally in the mark state (high level). SCI3 monitors the communication line and when it detects a space (low level), identifies this as a start bit and begins serial data communication. One transfer data character consists of a start bit (low level), followed by transmit/receive data (LSB-first format, starting from the least significant bit), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, synchronization is performed by the falling edge of the start bit during reception. The data is sampled on the 8th pulse of a clock with a frequency 16 times the bit period, so that the transfer data is latched at the center of each bit. Table 10-14 shows the 16 data transfer formats that can be set in asynchronous mode. The format is selected by the settings in the serial mode register (SMR). 285 Table 10-14 Data Transfer Formats (Asynchronous Mode) SMR CHR PE 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MP 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 STOP 0 1 0 1 0 S 1 0 S 1 S 0 1 0 1 0 1 0 1 S S S S S S S S 5-bit data 7-bit data 7-bit data 7-bit data 7-bit data 7-bit data 7-bit data 5-bit data 5-bit data P STOP STOP STOP Serial Data Transfer Format and Frame Length 1 S S 2 3 4 5 6 7 8 9 10 11 12 STOP 8-bit data 8-bit data STOP STOP S S 8-bit data 8-bit data MPB STOP MPB STOP STOP 8-bit data 8-bit data 5-bit data P STOP S P STOP STOP STOP STOP STOP STOP MPB STOP MPB STOP STOP P STOP P STOP STOP P STOP STOP Notation: Start bit S: STOP: Stop bit Parity bit P: MPB: Multiprocessor bit 286 b. Clock Either an internal clock generated by the baud rate generator or an external clock input at the SCK3X pin can be selected as the SCI3 transmit/receive clock. The selection is made by means of bit COM in SMR and bits SCE1 and CKE0 in SCR3. See table 10-12 for details on clock source selection. When an external clock is input at the SCK3X pin, the clock frequency should be 16 times the bit rate. When SCI3 operates on an internal clock, the clock can be output at the SCK 3X pin. In this case the frequency of the output clock is the same as the bit rate, and the phase is such that the clock rises at the center of each bit of transmit/receive data, as shown in figure 10-6. Clock Serial data 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 character (1 frame) Figure 10-6 Phase Relationship between Output Clock and Transfer Data (Asynchronous Mode) (8-bit data, parity, 2 stop bits) c. Data transfer operations * SCI3 initialization Before data is transferred on SCI3, bits TE and RE in SCR3 must first be cleared to 0, and then SCI3 must be initialized as follows. Note: If the operation mode or data transfer format is changed, bits TE and RE must first be cleared to 0. When bit TE is cleared to 0, bit TDRE is set to 1. Note that the RDRF, PER, FER, and OER flags and the contents of RDR are retained when RE is cleared to 0. When an external clock is used in asynchronous mode, the clock should not be stopped during operation, including initialization. When an external clock is used in synchronous mode, the clock should not be supplied during operation, including initialization. 287 Figure 10-7 shows an example of a flowchart for initializing SCI3. Start Clear bits TE and RE to 0 in SCR3 1 Set bits CKE1 and CKE0 2 Set data transfer format in SMR 1. Set clock selection in SCR3. Be sure to clear the other bits to 0. If clock output is selected in asynchronous mode, the clock is output immediately after setting bits CKE1 and CKE0. If clock output is selected for reception in synchronous mode, the clock is output immediately after bits CKE1, CKE0, and RE are set to 1. 2. Set the data transfer format in the serial mode register (SMR). 3. Write the value corresponding to the transfer rate in BRR. This operation is not necessary when an external clock is selected. 4. Wait for at least one bit period, then set bits TIE, RIE, MPIE, and TEIE in SCR3, and set bits RE and TE to 1 in PMR7. Setting bits TE and RE enables the TXD3x and RXD3x pins to be used. In asynchronous mode the mark state is established when transmitting, and the idle state waiting for a start bit when receiving. 3 Set value in BRR Wait No Has 1-bit period elapsed? Yes Set bits SPC31 and SPC32 to 1 in SPCR Set bits TIE, RIE, MPIE, and TEIE in SCR3, and set bits RE and TE to 1 in PMR7 4 End Figure 10-7 Example of SCI3 Initialization Flowchart 288 * Transmitting Figure 10-8 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3. Start Sets bits SPC31 and SPC32 to 1 in SPCR Read bit TDRE in SSR 1 No TDRE = 1? Yes Write transmit data to TDR 1. Read the serial status register (SSR) and check that bit TDRE is set to 1, then write transmit data to the transmit data register (TDR). When data is written to TDR, bit TDRE is cleared to 0 automatically. (After the TE bit is set to 1, one frame of 1s is output, then transmission is possible.) 2. When continuing data transmission, be sure to read TDRE = 1 to confirm that a write can be performed before writing data to TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. 3. If a break is to be output when data transmission ends, set the port PCR to 1 and clear the port PDR to 0, then clear bit TE in SCR3 to 0. 2 Continue data transmission? No Read bit TEND in SSR Yes TEND = 1? Yes 3 No Break output? Yes Set PDR = 0, PCR = 1 No Clear bit TE to 0 in SCR3 End Figure 10-8 Example of Data Transmission Flowchart (Asynchronous Mode) 289 SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made. Serial data is transmitted from the TXD3x pin using the relevant data transfer format in table 1014. When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data from TDR to TSR, and when the stop bit has been sent, starts transmission of the next frame. If bit TDRE is set to 1, bit TEND in SSR bit is set to 1the mark state, in which 1s are transmitted, is established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this time, a TEI request is made. Figure 10-9 shows an example of the operation when transmitting in asynchronous mode. Start bit Serial data 1 0 D0 D1 1 frame Transmit data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Transmit data D1 1 frame D7 Parity Stop bit bit 0/1 1 Mark state 1 TDRE TEND LSI TXI request operation User processing TDRE cleared to 0 Data written to TDR TXI request TEI request Figure 10-9 Example of Operation when Transmitting in Asynchronous Mode (8-bit data, parity, 1 stop bit) 290 * Receiving Figure 10-10 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start 1 Read bits OER, PER, FER in SSR OER + PER + FER = 1? No 2 Read bit RDRF in SSR Yes 1. Read bits OER, PER, and FER in the serial status register (SSR) to determine if there is an error. If a receive error has occurred, execute receive error processing. 2. Read SSR and check that bit RDRF is set to 1. If it is, read the receive data in RDR. When the RDR data is read, bit RDRF is cleared to 0 automatically. 3. When continuing data reception, finish reading of bit RDRF and RDR before receiving the stop bit of the current frame. When the data in RDR is read, bit RDRF is cleared to 0 automatically. RDRF = 1? Yes Read receive data in RDR No 4 Receive error processing 3 Continue data reception? No Yes (A) Clear bit RE to 0 in SCR3 End Figure 10-10 Example of Data Reception Flowchart (Asynchronous Mode) 291 4 Start receive error processing Overrun error processing OER = 1? No FER = 1? No PER = 1? No Clear bits OER, PER, FER to 0 in SSR Parity error processing Yes Framing error processing Yes Yes Break? No 4. If a receive error has occurred, read bits OER, PER, and FER in SSR to identify the error, and after carrying out the necessary error processing, ensure that bits OER, PER, and FER are all cleared to 0. Yes Reception cannot be resumed if any of these bits is set to 1. In the case of a framing error, a break can be detected by reading the value of the RXD3x pin. (A) End of receive error processing Figure 10-10 Example of Data Reception Flowchart (Asynchronous Mode) (cont) 292 SCI3 operates as follows when receiving data. SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal synchronization and begins reception. Reception is carried out in accordance with the relevant data transfer format in table 10-14. The received data is first placed in RSR in LSB-to-MSB order, and then the parity bit and stop bit(s) are received. SCI3 then carries out the following checks. * Parity check SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even) set in bit PM in the serial mode register (SMR). * Stop bit check SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked. * Status check SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from RSR to RDR. If no receive error is found in the above checks, bit RDRF is set to 1, and the receive data is stored in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the error checks identify a receive error, bit OER, PER, or FER is set to 1 depending on the kind of error. Bit RDRF retains its state prior to receiving the data. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested. Table 10-15 shows the conditions for detecting a receive error, and receive data processing. Note: No further receive operations are possible while a receive error flag is set. Bits OER, FER, PER, and RDRF must therefore be cleared to 0 before resuming reception. Table 10-15 Receive Error Detection Conditions and Receive Data Processing Receive Error Abbreviation Detection Conditions Overrun error OER When the next date receive operation is completed while bit RDRF is still set to 1 in SSR When the stop bit is 0 Receive Data Processing Receive data is not transferred from RSR to RDR Receive data is transferred from RSR to RDR Framing error Parity error FER PER When the parity (odd or even) set Receive data is transferred in SMR is different from that of the from RSR to RDR received data 293 Figure 10-11 shows an example of the operation when receiving in asynchronous mode. Start bit Serial data 1 0 D0 D1 1 frame Receive data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Receive data D1 1 frame D7 Parity Stop bit bit 0/1 0 Mark state (idle state) 1 RDRF FER LSI operation User processing RXI request RDRF cleared to 0 RDR data read 0 start bit detected ERI request in response to framing error Framing error processing Figure 10-11 Example of Operation when Receiving in Asynchronous Mode (8-bit data, parity, 1 stop bit) 3. Operation in Synchronous Mode In synchronous mode, SCI3 transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. SCI3 has separate transmission and reception units, allowing full-duplex communication with a shared clock. As the transmission and reception units are both double-buffered, data can be written during transmission and read during reception, making possible continuous transmission and reception. 294 a. Data transfer format The general data transfer format in synchronous communication is shown in figure 10-12. * Serial clock LSB Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 * Don't care 8 bits One transfer data unit (character or frame) Don't care Note: High level except in continuous transmission/reception Figure 10-12 Data Format in Synchronous Communication In synchronous communication, data on the communication line is output from one falling edge of the serial clock until the next falling edge. Data confirmation is guaranteed at the rising edge of the serial clock. One transfer data character begins with the LSB and ends with the MSB. After output of the MSB, the communication line retains the MSB state. When receiving in synchronous mode, SCI3 latches receive data at the rising edge of the serial clock. The data transfer format uses a fixed 8-bit data length. Parity and multiprocessor bits cannot be added. b. Clock Either an internal clock generated by the baud rate generator or an external clock input at the SCK3x pin can be selected as the SCI3 serial clock. The selection is made by means of bit COM in SMR and bits CKE1 and CKE0 in SCR3. See table 10-12 for details on clock source selection. When SCI3 operates on an internal clock, the serial clock is output at the SCK3x pin. Eight pulses of the serial clock are output in transmission or reception of one character, and when SCI3 is not transmitting or receiving, the clock is fixed at the high level. 295 c. Data transfer operations * SCI3 initialization Data transfer on SCI3 first of all requires that SCI3 be initialized as described in "SCI initialization" under 10.3.3, 2. c. Data transfer operations, and shown in figure 10-7. * Transmitting Figure 10-13 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3. Start Sets bits SPC31 and SPC32 to 1 in SPCR 1 Read bit TDRE in SSR No TDRE = 1? Yes Write transmit data to TDR 1. Read the serial status register (SSR) and check that bit TDRE is set to 1, then write transmit data to the transmit data register (TDR). When data is written to TDR, bit TDRE is cleared to 0 automatically, the clock is output, and data transmission is started. When clock output is selected, the clock is output and data transmission started when data is written to TDR. 2. When continuing data transmission, be sure to read TDRE = 1 to confirm that a write can be performed before writing data to TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. 2 Continue data transmission? No Read bit TEND in SSR Yes TEND = 1? Yes Clear bit TE to 0 in SCR3 No End Figure 10-13 Example of Data Transmission Flowchart (Synchronous Mode) 296 SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made. When clock output mode is selected, SCI3 outputs 8 serial clock pulses. When an external clock is selected, data is output in synchronization with the input clock. Serial data is transmitted from the TXD3x pin in order from the LSB (bit 0) to the MSB (bit 7). When the MSB (bit 7) is sent, checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data from TDR to TSR, and starts transmission of the next frame. If bit TDRE is set to 1, SCI3 sets bit TEND to 1 in SSR, and after sending the MSB (bit 7), retains the MSB state. If bit TEIE in SCR3 is set to 1 at this time, a TEI request is made. After transmission ends, the SCK pin is fixed at the high level. Note: Transmission is not possible if an error flag (OER, FER, or PER) that indicates the data reception status is set to 1. Check that these error flags are all cleared to 0 before a transmit operation. Figure 10-14 shows an example of the operation when transmitting in synchronous mode. Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 1 frame TDRE TEND TXI request LSI operation User processing TDRE cleared to 0 Data written to TDR TXI request 1 frame TEI request Figure 10-14 Example of Operation when Transmitting in Synchronous Mode 297 * Receiving Figure 10-15 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start 1 Read bit OER in SSR 1. Read bit OER in the serial status register (SSR) to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Yes 2. Read SSR and check that bit RDRF is set to 1. If it is, read the receive data in RDR. When the RDR data is read, bit RDRF is cleared to 0 automatically. 3. When continuing data reception, finish reading of bit RDRF and RDR before receiving the MSB (bit 7) of the current frame. When the data in RDR is read, bit RDRF is cleared to 0 automatically. 4. If an overrun error has occurred, read bit OER in SSR, and after carrying out the necessary error processing, clear bit OER to 0. Reception cannot be resumed if bit OER is set to 1. Overrun error processing OER = 1? No 2 Read bit RDRF in SSR RDRF = 1? Yes Read receive data in RDR No 4 3 Continue data reception? No Clear bit RE to 0 in SCR3 Yes 4 Start overrun error processing End Overrun error processing Clear bit OER to 0 in SSR End of overrun error processing Figure 10-15 Example of Data Reception Flowchart (Synchronous Mode) 298 SCI3 operates as follows when receiving data. SCI3 performs internal synchronization and begins reception in synchronization with the serial clock input or output. The received data is placed in RSR in LSB-to-MSB order. After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from RSR to RDR. If this check shows that there is no overrun error, bit RDRF is set to 1, and the receive data is stored in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the check identifies an overrun error, bit OER is set to 1. Bit RDRF remains set to 1. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested. See table 10-15 for the conditions for detecting a receive error, and receive data processing. Note: No further receive operations are possible while a receive error flag is set. Bits OER, FER, PER, and RDRF must therefore be cleared to 0 before resuming reception. Figure 10-16 shows an example of the operation when receiving in synchronous mode. Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 1 frame RDRF OER LSI operation User processing RXI request RDRE cleared to 0 RDR data read RXI request 1 frame ERI request in response to overrun error RDR data has not been read (RDRF = 1) Overrun error processing Figure 10-16 Example of Operation when Receiving in Synchronous Mode 299 * Simultaneous transmit/receive Figure 10-17 shows an example of a flowchart for a simultaneous transmit/receive operation. This procedure should be followed for simultaneous transmission/reception after initializing SCI3. Start Sets bits SPC31 and SPC32 to 1 in SPCR 1 Read bit TDRE in SSR TDRE = 1? Yes Write transmit data to TDR No 1. Read the serial status register (SSR) and check that bit TDRE is set to 1, then write transmit data to the transmit data register (TDR). When data is written to TDR, bit TDRE is cleared to 0 automatically. 2. Read SSR and check that bit RDRF is set to 1. If it is, read the receive data in RDR. When the RDR data is read, bit RDRF is cleared to 0 automatically. 3. When continuing data transmission/reception, finish reading of bit RDRF and RDR before receiving the MSB (bit 7) of the current frame. Before receiving the MSB (bit 7) of the current frame, also read TDRE = 1 to confirm that a write can be performed, then write data to TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically, and when the data in RDR is read, bit RDRF is cleared to 0 automatically. 4. If an overrun error has occurred, read bit OER in SSR, and after carrying out the necessary error processing, clear bit OER to 0. Transmission and reception cannot be resumed if bit OER is set to 1. See figure 10-18 for details on overrun error processing. Read bit OER in SSR OER = 1? No Read bit RDRF in SSR Yes 2 RDRF = 1? Yes Read receive data in RDR No 4 Overrun error processing 3 Continue data transmission/reception? No Clear bits TE and RE to 0 in SCR3 Yes Notes: 1. When switching from transmission to simultaneous transmission/reception, check that SCI3 has finished transmitting and that bits TDRE and TEND are set to 1, clear bit TE to 0, and then set bits TE and RE to 1. 2. When switching from reception to simultaneous transmission/reception, check that SCI3 has finished receiving, clear bit RE to 0, then check that bit RDRF and the error flags (OER, FER, and PER) are cleared to 0, and finally set bits TE and RE to 1. End Figure 10-17 Example of Simultaneous Data Transmission/Reception Flowchart (Synchronous Mode) 300 4. Multiprocessor Communication Function The multiprocessor communication function enables data to be exchanged among a number of processors on a shared communication line. Serial data communication is performed in asynchronous mode using the multiprocessor format (in which a multiprocessor bit is added to the transfer data). In multiprocessor communication, each receiver is assigned its own ID code. The serial communication cycle consists of two cycles, an ID transmission cycle in which the receiver is specified, and a data transmission cycle in which the transfer data is sent to the specified receiver. These two cycles are differentiated by means of the multiprocessor bit, 1 indicating an ID transmission cycle, and 0, a data transmission cycle. The sender first sends transfer data with a 1 multiprocessor bit added to the ID code of the receiver it wants to communicate with, and then sends transfer data with a 0 multiprocessor bit added to the transmit data. When a receiver receives transfer data with the multiprocessor bit set to 1, it compares the ID code with its own ID code, and if they are the same, receives the transfer data sent next. If the ID codes do not match, it skips the transfer data until data with the multiprocessor bit set to 1 is sent again. In this way, a number of processors can exchange data among themselves. Figure 10-18 shows an example of communication between processors using the multiprocessor format. 301 Sender Communication line Receiver A (ID = 01) Receiver B (ID = 02) Receiver C (ID = 03) Receiver D (ID = 04) Serial data H'01 (MPB = 1) ID transmission cycle (specifying the receiver) H'AA (MPB = 0) Data transmission cycle (sending data to the receiver specified buy the ID) MPB: Multiprocessor bit Figure 10-18 Example of Inter-Processor Communication Using Multiprocessor Format (Sending data H'AA to receiver A) There is a choice of four data transfer formats. If a multiprocessor format is specified, the parity bit specification is invalid. See table 10-14 for details. For details on the clock used in multiprocessor communication, see 10.3.3, 2. Operation in Asynchronous Mode. * Multiprocessor transmitting Figure 10-19 shows an example of a flowchart for multiprocessor data transmission. This procedure should be followed for multiprocessor data transmission after initializing SCI3. 302 Start Sets bits SPC31 and SPC32 to 1 in SPCR 1 Read bit TDRE in SSR TDRE = 1? Yes Set bit MPDT in SSR No 1. Read the serial status register (SSR) and check that bit TDRE is set to 1, then set bit MPBT in SSR to 0 or 1 and write transmit data to the transmit data register (TDR). When data is written to TDR, bit TDRE is cleared to 0 automatically. 2. When continuing data transmission, be sure to read TDRE = 1 to confirm that a write can be performed before writing data to TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. 3. If a break is to be output when data transmission ends, set the port PCR to 1 and clear the port PDR to 0, then clear bit TE in SCR3 to 0. Write transmit data to TDR 2 Continue data transmission? No Read bit TEND in SSR Yes TEND = 1? Yes No 3 Break output? Yes No Set PDR = 0, PCR = 1 Clear bit TE to 0 in SCR3 End Figure 10-19 Example of Multiprocessor Data Transmission Flowchart 303 SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made. Serial data is transmitted from the TXD pin using the relevant data transfer format in table 10-14. When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data from TDR to TSR, and when the stop bit has been sent, starts transmission of the next frame. If bit TDRE is set to 1 bit TEND in SSR bit is set to 1, the mark state, in which 1s are transmitted, is established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this time, a TEI request is made. Figure 10-20 shows an example of the operation when transmitting using the multiprocessor format. Start bit Serial data 1 0 D0 D1 1 frame Transmit data D7 Stop Start bit bit 1 0 D0 Transmit data D1 1 frame Stop bit 1 Mark state 1 MPB 0/1 MPB 0/1 D7 TDRE TEND LSI TXI request operation User processing TDRE cleared to 0 Data written to TDR TXI request TEI request Figure 10-20 Example of Operation when Transmitting using Multiprocessor Format (8-bit data, multiprocessor bit, 1 stop bit) * Multiprocessor receiving Figure 10-21 shows an example of a flowchart for multiprocessor data reception. This procedure should be followed for multiprocessor data reception after initializing SCI3. 304 Start 1. Set bit MPIE to 1 in SCR3. 2. Read bits OER and FER in the serial status register (SSR) to determine if there is an error. If a receive error has occurred, execute receive error processing. 3. Read SSR and check that bit RDRF is set to 1. If it is, read the receive data in RDR and compare it with this receiver's own ID. If the ID is not this receiver's, set bit MPIE to 1 again. When the RDR data is read, bit RDRF is cleared to 0 automatically. 4. Read SSR and check that bit RDRF is set to 1, then read the data in RDR. 5. If a receive error has occurred, read bits OER and FER in SSR to identify the error, and after carrying out the necessary error processing, ensure that bits OER and FER are both cleared to 0. Reception cannot be resumed if either of these bits is set to 1. In the case of a framing error, a break can be detected by reading the value of the RXD3x pin. 1 Set bit MPIE to 1 in SCR3 2 Read bits OER and FER in SSR Yes OER + FER = 1? No 3 Read bit RDRF in SSR RDRF = 1? Yes Read receive data in RDR No Own ID? Yes Read bits OER and FER in SSR No OER + FER = 1? No 4 Read bit RDRF in SSR Yes RDRF = 1? Yes Read receive 4 data in RDR No 5 Receive error processing Continue data reception? No Clear bit RE to 0 in SCR3 End Yes (A) Figure 10-21 Example of Multiprocessor Data Reception Flowchart 305 Start receive error processing Overrun error processing OER = 1? No FER = 1? No Clear bits OER and FER to 0 in SSR Yes Yes Yes Break? No Framing error processing End of receive error processing (A) Figure 10-21 Example of Multiprocessor Data Reception Flowchart (cont) Figure 10-22 shows an example of the operation when receiving using the multiprocessor format. 306 Start bit Serial data 1 0 D0 Receive data (ID1) D1 1 frame D7 MPB 1 Stop Start bit bit 1 0 D0 Receive data (Data1) D1 1 frame D7 MPB 0 Stop bit 1 Mark state (idle state) 1 MPIE RDRF RDR value LSI operation User processing RXI request MPIE cleared to 0 RDRF cleared to 0 RDR data read When data is not this receiver's ID, bit MPIE is set to 1 again ID1 No RXI request RDR retains previous state (a) When data does not match this receiver's ID Start bit Serial data 1 0 D0 Receive data (ID2) D1 1 frame D7 MPB 1 Stop Start bit bit 1 0 D0 Receive data (Data2) D1 1 frame D7 MPB 0 Stop bit 1 Mark state (idle state) 1 MPIE RDRF RDR value LSI operation User processing ID1 ID2 Data2 RXI request MPIE cleared to 0 RDRF cleared to 0 RDR data read RXI request RDRF cleared to 0 RDR data read Bit MPIE set to 1 again When data is this receiver's ID, reception is continued (b) When data matches this receiver's ID Figure 10-22 Example of Operation when Receiving using Multiprocessor Format (8-bit data, multiprocessor bit, 1 stop bit) 307 10.3.4 Interrupts SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and three receive error interrupts (overrun error, framing error, and parity error). These interrupts have the same vector address. The various interrupt requests are shown in table 10-16. Table 10-16 SCI3 Interrupt Requests Interrupt Abbreviation RXI TXI TEI ERI Interrupt Request Interrupt request initiated by receive data full flag (RDRF) Interrupt request initiated by transmit data empty flag (TDRE) Interrupt request initiated by transmit end flag (TEND) Interrupt request initiated by receive error flag (OER, FER, PER) Vector Address H'0022/H'0024 Each interrupt request can be enabled or disabled by means of bits TIE and RIE in SCR3. When bit TDRE is set to 1 in SSR, a TXI interrupt is requested. When bit TEND is set to 1 in SSR, a TEI interrupt is requested. These two interrupts are generated during transmission. The initial value of bit TDRE in SSR is 1. Therefore, if the transmit data empty interrupt request (TXI) is enabled by setting bit TIE to 1 in SCR3 before transmit data is transferred to TDR, a TXI interrupt will be requested even if the transmit data is not ready. Also, the initial value of bit TEND in SSR is 1. Therefore, if the transmit end interrupt request (TEI) is enabled by setting bit TEIE to 1 in SCR3 before transmit data is transferred to TDR, a TEI interrupt will be requested even if the transmit data has not been sent. Effective use of these interrupt requests can be made by having processing that transfers transmit data to TDR carried out in the interrupt service routine. To prevent the generation of these interrupt requests (TXI and TEI), on the other hand, the enable bits for these interrupt requests (bits TIE and TEIE) should be set to 1 after transmit data has been transferred to TDR. When bit RDRF is set to 1 in SSR, an RXI interrupt is requested, and if any of bits OER, PER, and FER is set to 1, an ERI interrupt is requested. These two interrupt requests are generated during reception. For further details, see 3.3, Interrupts. 308 10.3.5 Application Notes The following points should be noted when using SCI3. 1. Relation between writes to TDR and bit TDRE Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1. Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost of it has not yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed dependably, you should first check that bit TDRE is set to 1, then write the transmit data to TDR once only (not two or more times). 2. Operation when a number of receive errors occur simultaneously If a number of receive errors are detected simultaneously, the status flags in SSR will be set to the states shown in table 10-17. If an overrun error is detected, data transfer from RSR to RDR will not be performed, and the receive data will be lost. Table 10-17 SSR Status Flag States and Receive Data Transfer SSR Status Flags RDRF* OER 1 0 0 1 1 0 1 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Transfer RSR RDR Receive Error Status x Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error * * x x * x * : Receive data is transferred from RSR to RDR. x: Receive data is not transferred from RSR to RDR. Note: * Bit RDRF retains its state prior to data reception. However, note that if RDR is read after an overrun error has occurred in a frame because reading of the receive data in the previous frame was delayed, RDRF will be cleared to 0. 309 3. Break detection and processing When a framing error is detected, a break can be detected by reading the value of the RXD3X pin directly. In a break, the input from the RXD 3X pin becomes all 0s, with the result that bit FER is set and bit PER may also be set. SCI3 continues the receive operation even after receiving a break. Note, therefore, that even though bit FER is cleared to 0 it will be set to 1 again. 4. Mark state and break detection When bit TE is cleared to 0, the TXD3X pin functions as an I/O port whose input/output direction and level are determined by PDR and PCR. This fact can be used to set the TXD3X pin to the mark state, or to detect a break during transmission. To keep the communication line in the mark state (1 state) until bit TE is set to 1, set PCR = 1 and PDR = 1. Since bit TE is cleared to 0 at this time, the TXD3X pin functions as an I/O port and 1 is output. To detect a break, clear bit TE to 0 after setting PCR = 1 and PDR = 0. When bit TE is cleared to 0, the transmission unit is initialized regardless of the current transmission state, the TXD 3X pin functions as an I/O port, and 0 is output from the TXD3X pin. 5. Receive error flags and transmit operation (synchronous mode only) When a receive error flag (OER, PER, or FER) is set to 1, transmission cannot be started even if bit TDRE is cleared to 0. The receive error flags must be cleared to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if bit RE is cleared to 0. 6. Receive data sampling timing and receive margin in asynchronous mode In asynchronous mode, SCI3 operates on a basic clock with a frequency 16 times the transfer rate. When receiving, SCI3 performs internal synchronization by sampling the falling edge of the start bit with the basic clock. Receive data is latched internally at the 8th rising edge of the basic clock. This is illustrated in figure 10-23. 310 16 clock pulses 8 clock pulses 0 7 15 0 7 15 0 Internal basic clock Receive data (RXD3x) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 10-23 Receive Data Sampling Timing in Asynchronous Mode Consequently, the receive margin in asynchronous mode can be expressed as shown in equation (1). M ={(0.5 - 1 ) - D - 0.5 - (L - 0.5) F} 5 100 [%] 2N N where M: Receive margin (%) N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0.5 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock frequency deviation Substituting 0 for F (absolute value of clock frequency deviation) and 0.5 for D (clock duty) in equation (1), a receive margin of 46.875% is given by equation (2). When D = 0.5 and F = 0, M = {0.5 -- 1/(2 x 16)} x 100 [%] = 46.875% ..... Equation (2) However, this is only a computed value, and a margin of 20% to 30% should be allowed when carrying out system design. ..... Equation (1) 311 7. Relation between RDR reads and bit RDRF In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this indicates that an overrun error has occurred. When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if bit RDR is read more than once, the second and subsequent read operations will be performed while bit RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is cleared to 0, if the read operation coincides with completion of reception of a frame, the next frame of data may be read. This is illustrated in figure 10-24. Frame 1 Frame 2 Frame 3 Communication line Data 1 Data 2 Data 3 RDRF RDR Data 1 Data 2 (A) RDR read (B) RDR read Data 1 is read at point (A) Data 2 is read at point (B) Figure 10-24 Relation between RDR Read Timing and Data In this case, only a single RDR read operation (not two or more) should be performed after first checking that bit RDRF is set to 1. If two or more reads are performed, the data read the first time should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is sufficient margin in an RDR read operation before reception of the next frame is completed. To be precise in terms of timing, the RDR read should be completed before bit 7 is transferred in synchronous mode, or before the STOP bit is transferred in asynchronous mode. 8. Transmission and Reception Operation at State Transition Make sure state transition operation is performed after transmission and reception operations are completed. 312 9. Cautions on Switching of SCK3X Pin Function If the function of the SCK3X pin is switched from clock output to I/O port after using the SCI3 in clock synchronization mode, the low level is output in a moment (1/2 of the system clock o) at the SCK3X pin function switching. This momentary low level output can be avoided in either of the following two methods: a. When disabling SCK3X pin clock output When stopping signal transmission, clear the bits TE and RE in SCR3, and set the CKE1 bit to 1 and the CKE0 bit to 0 simultaneously with a single command. In this case, use the COM bit in SMR set at 1. This means it cannot be used as an I/O port. Also, to avoid intermediate potential from being applied to the SCK3X pin, pull up the line connected to the SCK3X pin to VCC potential with a resistance, or supply an output from other devices. b. When switching the SCK3X pin function from clock output to I/O port When stopping signal transmission, (1) Clear the bits TE and RE in SCR3, and set the CKE1 bit to 1 and the CKE0 bit to 0 simultaneously with a single command. (2) Then, clear the COM bit in SMR to 0. (3) Finally, clear the bits CKE1 and CKE0 in SCR3 to 0. Avoid intermediate potential from being applied to the SCK3X pin. 10. Setting in Subactive and Subsleep Modes In subactive or subsleep mode, SCI3 can be used only when the oW/2 is selected as the CPU clock. Set the SA1 bit in SYSCR2 to 1. 313 314 Section 11 A/D Converter 11.1 Overview The H8/3937 Series and H8/3937R Series include on-chip a resistance-ladder-based successiveapproximation analog-to-digital converter, and can convert up to 8 channels of analog input. 11.1.1 Features The A/D converter has the following features. * * * * * * * 10-bit resolution 8 input channels Conversion time: approx. 12.4 s per channel (at 5 MHz operation) Built-in sample-and-hold function Interrupt requested on completion of A/D conversion A/D conversion can be started by external trigger input Use of module standby mode enables this module to be placed in standby mode independently when not used. 315 11.1.2 Block Diagram Figure 11-1 shows a block diagram of the A/D converter. ADTRG AMR AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 AVCC + Comparator - Control logic AVCC Reference voltage AVSS AVSS ADRRH ADRRL Notation: AMR: A/D mode register ADSR: A/D start register ADRR: A/D result register IRRAD: A/D conversion end interrupt request flag Figure 11-1 Block Diagram of the A/D Converter 316 Internal data bus IRRAD Multiplexer ADSR 11.1.3 Pin Configuration Table 11-1 shows the A/D converter pin configuration. Table 11-1 Pin Configuration Name Analog power supply Analog ground Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5 Analog input 6 Analog input 7 External trigger input Abbrev. AVCC AVSS AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input Function Power supply and reference voltage of analog part Ground and reference voltage of analog part Analog input channel 0 Analog input channel 1 Analog input channel 2 Analog input channel 3 Analog input channel 4 Analog input channel 5 Analog input channel 6 Analog input channel 7 External trigger input for starting A/D conversion 11.1.4 Register Configuration Table 11-2 shows the A/D converter register configuration. Table 11-2 Register Configuration Name A/D mode register A/D start register A/D result register H A/D result register L Clock stop register 1 Abbrev. AMR ADSR ADRRH ADRRL CKSTPRT1 R/W R/W R/W R R R/W Initial Value H'30 H'7F Not fixed Not fixed H'FF Address H'FFC6 H'FFC7 H'FFC4 H'FFC5 H'FFFA 317 11.2 11.2.1 Bit Register Descriptions A/D Result Registers (ADRRH, ADRRL) 7 6 5 4 3 2 1 0 7 6 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 -- -- 0 -- -- ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 Initial value Read/Write Not Not fixed fixed R R Not Not Not Not Not Not Not Not fixed fixed fixed fixed fixed fixed fixed fixed R R R R R R R R -- -- -- -- -- -- ADRRH ADRRL ADRRH and ADRRL together comprise a 16-bit read-only register for holding the results of analog-to-digital conversion. The upper 8 bits of the data are held in ADRRH, and the lower 2 bits in ADRRL. ADRRH and ADRRL can be read by the CPU at any time, but the ADRRH and ADRRL values during A/D conversion are not fixed. After A/D conversion is complete, the conversion result is stored as 10-bit data, and this data is held until the next conversion operation starts. ADRRH and ADRRL are not cleared on reset. 11.2.2 Bit Initial value Read/Write A/D Mode Register (AMR) 7 CKS 0 R/W 6 TRGE 0 R/W 5 -- 1 -- 4 -- 1 -- 3 CH3 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W AMR is an 8-bit read/write register for specifying the A/D conversion speed, external trigger option, and the analog input pins. Upon reset, AMR is initialized to H'30. 318 Bit 7: Clock select (CKS) Bit 7 sets the A/D conversion speed. Bit 7 CKS 0 1 Note: * Conversion Period 62/o (initial value) 31/o Conversion Time o = 1 MHz 62 s 31 s o = 5 MHz 12.4 s -- Operation is not guaranteed if the conversion time is less than 12.4 s. Set bit 7 for a value of at least 12.4 s. Bit 6: External trigger select (TRGE) Bit 6 enables or disables the start of A/D conversion by external trigger input. Bit 6 TRGE 0 1 Note: * Description Disables start of A/D conversion by external trigger (initial value) Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG* The external trigger (ADTRG) edge is selected by bit INTEG4 of IEGR. See 1. IRQ edge select register (IEGR) in 3.3.2 for details. Bits 5 and 4: Reserved bits Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified. 319 Bits 3 to 0: Channel select (CH3 to CH0) Bits 3 to 0 select the analog input channel. The channel selection should be made while bit ADSF is cleared to 0. Bit 3 CH3 0 0 0 0 0 1 1 1 1 1 Bit 2 CH2 0 1 1 1 1 0 0 0 0 1 Bit 1 CH1 * 0 0 1 1 0 0 1 1 * Bit 0 CH0 * 0 1 0 1 0 1 0 1 * Analog Input Channel No channel selected AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 Reserved *: Don't care (initial value) 11.2.3 Bit A/D Start Register (ADSR) 7 ADSF 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value Read/Write The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D conversion. A/D conversion is started by writing 1 to the A/D start flag (ADSF) or by input of the designated edge of the external trigger signal, which also sets ADSF to 1. When conversion is complete, the converted data is set in ADRRH and ADRRL, and at the same time ADSF is cleared to 0. 320 Bit 7: A/D start flag (ADSF) Bit 7 controls and indicates the start and end of A/D conversion. Bit 7 ADSF 0 Description Read: Indicates the completion of A/D conversion Write: Stops A/D conversion 1 Read: Indicates A/D conversion in progress Write: Starts A/D conversion (initial value) Bits 6 to 0: Reserved bits Bits 6 to 0 are reserved; they are always read as 1, and cannot be modified. 11.2.4 Bit Initial value Read/Write Clock Stop Register 1 (CKSTPR1) 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to the A/D converter is described here. For details of the other bits, see the sections on the relevant modules. Bit 4: A/D converter module standby mode control (ADCKSTP) Bit 4 controls setting and clearing of module standby mode for the A/D converter. ADCKSTP 0 1 Description A/D converter is set to module standby mode A/D converter module standby mode is cleared (initial value) 321 11.3 11.3.1 Operation A/D Conversion Operation The A/D converter operates by successive approximations, and yields its conversion result as 10bit data. A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete. The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1. An A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 2 (IENR2) is set to 1. If the conversion time or input channel needs to be changed in the A/D mode register (AMR) during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation, in order to avoid malfunction. 11.3.2 Start of A/D Conversion by External Trigger Input The A/D converter can be made to start A/D conversion by input of an external trigger signal. External trigger input is enabled at pin ADTRG when bit IRQ4 in PMR1 is set to 1 and bit TRGE in AMR is set to 1. Then when the input signal edge designated in bit IEG4 of interrupt edge select register (IEGR) is detected at pin ADTRG, bit ADSF in ADSR will be set to 1, starting A/D conversion. Figure 11-2 shows the timing. o Pin ADTRG (when bit IEG4 = 0) ADSF A/D conversion Figure 11-2 External Trigger Input Timing 322 11.3.3 A/D Converter Operation Modes A/D converter operation modes are shown in table 11-3. Table 11-3 A/D Converter Operation Modes Operation Mode AMR ADSR ADRRH ADRRL Module Standby Held Held Held Held Reset Reset Reset Held* Held* Active Sleep Watch Held Held Held Held Subactive Held Held Held Held Subsleep Held Held Held Held Standby Held Held Held Held Functions Functions Functions Functions Functions Functions Functions Functions Note: * Undefined in a power-on reset. 11.4 Interrupts When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request register 2 (IRR2) is set to 1. A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt enable register 2 (IENR2). For further details see 3.3, Interrupts. 11.5 Typical Use An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as the analog input channel. Figure 11-3 shows the operation timing. 1. Bits CH3 to CH0 of the A/D mode register (AMR) are set to 0101, making pin AN1 the analog input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is started by setting bit ADSF to 1. 2. When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion result is stored is stored in ADRRH and ADRRL. At the same time ADSF is cleared to 0, and the A/D converter goes to the idle state. 3. Bit IENAD = 1, so an A/D conversion end interrupt is requested. 4. The A/D interrupt handling routine starts. 5. The A/D conversion result is read and processed. 323 6. The A/D interrupt handling routine ends. If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place. Figures 11-4 and 11-5 show flow charts of procedures for using the A/D converter. Interrupt (IRRAD) Set * IENAD ADSF A/D conversion starts Set * Set * Channel 1 (AN1) operation state Idle A/D conversion (1) Idle A/D conversion (2) Idle Read conversion result ADRRH ADRRL Note: * ( ) indicates instruction execution by software. A/D conversion result (1) Read conversion result A/D conversion result (2) Figure 11-3 Typical A/D Converter Operation Timing 324 Start Set A/D conversion speed and input channel Disable A/D conversion end interrupt Start A/D conversion Read ADSR No ADSF = 0? Yes Read ADRRH/ADRRL data Yes Perform A/D conversion? No End Figure 11-4 Flow Chart of Procedure for Using A/D Converter (Polling by Software) 325 Start Set A/D conversion speed and input channels Enable A/D conversion end interrupt Start A/D conversion A/D conversion end interrupt? No Yes Clear bit IRRAD to 0 in IRR2 Read ADRRH/ADRRL data Yes Perform A/D conversion? No End Figure 11-5 Flow Chart of Procedure for Using A/D Converter (Interrupts Used) 326 11.6 Application Notes * Data in ADRRH and ADRRL should be read only when the A/D start flag (ADSF) in the A/D start register (ADSR) is cleared to 0. * Changing the digital input signal at an adjacent pin during A/D conversion may adversely affect conversion accuracy. * When A/D conversion is started after clearing module standby mode, wait for 10 o clock cycles before starting. * In active mode and sleep mode, the analog power supply current (AISTOP1) flows in the ladder resistance even when the A/D converter is on standby. Therefore, if the A/D converter is not used, it is recommended that AV CC be connected to the system power supply and the ADCKSTP (A/D converter module standby mode control) bit be cleared to 0 in clock stop register 1 (CKSTPR1). 327 328 Section 12 FLEXTM Roaming Decoder II The contents of this section apply to the FLEXTM Roaming Decoder. Note that underlining in the text indicates differences in specification from the FLEXTM Non-Roaming Decoder. 12.1 Overview Its primary function is to process information received and demodulated from a FLEX radio paging channel, select messages addressed to the paging device and communicate the message information to the host. The FLEX decoder also operates the paging receiver in an efficient power consumption mode and enables the host to operate in a low power mode when monitoring a single channel for message information. 12.1.1 * * * * * * * * * * * * * * * * * * * Features FLEX TM paging protocol decoder 16 programmable user address words 16 fixed temporary addresses 16 operator messaging addresses 1600, 3200, and 6400 bits per second decoding Any-phase or single-phase decoding Uses standard Serial Peripheral Interface (SPI) in slave mode Allows low current STOP mode operation of host processor Highly programmable receiver control Real time clock time base FLEX fragmentation and group messaging support Real time clock over-the-air update support Compatible with synthesized receivers SSID and NID Roaming support Low Battery Indication (External detector) Backward compatible to the standard and roaming FLEX decoders Internal demodulator and data slicer Improved battery savings via partial correlation and intermittent receiver clock Full support for revision 1.9 of the FLEX protocol Additional Support: FLEX System Software from Motorola is a family of software components for building world-class products incorporating messaging capabilities. FLEXstackTM Software is specifically designed to support the FLEXTM Roaming Decoder II IC. FLEXstack Software runs on a product's host processor and takes care of communicating with the FLEX decoder, acquiring 329 the proper FLEX channel, and fully interpreting the code words that are passed to the host from the FLEX decoder. Additional Information: Additional Information on the FLEXTM protocol decoder chip set and FLEXstackTM software can be found at the following website: http://www.hitachi.co.jp/Sicd/English/Products/micom/stack/stack.html. 12.1.2 System Block Diagram Synthesizer Programming Control Receiver Receiver Control This LSI S0/IFIN User Interface 38.4 or 40 kHz clock Low Battery Detector LOBAT 160 kHz Oscillator Figure 12-1 Example Block Diagram Using Internal Demodulator When configured to use the internal demodulator, the FLEX decoder connects to a receiver capable of generating a limited (i.e. 1-bit digitized) 455 kHz or 140 kHz IF signal. In this mode, the FLEX decoder has 7 receiver control lines used for warming up and shutting down a receiver in stages. The FLEX decoder has the ability to detect a low battery signal during the receiver control sequences. It interfaces to a host MCU through a standard SPI. It has a 1 minute timer that offers low power support for a time of day function on the host. When using the internal demodulator, the oscillator frequency (or external clock) must be 160 kHz. The CLKOUT signal can be programmed to be either a 38.4 kHz signal created by fractionally dividing the oscillator clock, or a 40 kHz signal creating by dividing the oscillator clock by 4. 330 Synthesizer Programming Control Receiver Audio Receiver Control This LSI EXTS1 User Interface 38.4 clock Audio to Digital Convertor EXTS0 76.8 kHz Oscillator Low Battery Detector LOBAT Figure 12-2 Example Block Diagram Using External Demodulator The FLEX decoder can also be configured to connect to a receiver capable of converting a 4 level audio signal into a 2 bit digital signal. In this mode, the FLEX decoder has 8 receiver control lines used for warming up and shutting down a receiver in stages. It also includes configuration settings for the two post detection filter bandwidths required to decode the two symbol rates of the FLEX signal. Also when using an external demodulator, the oscillator (or external clock) must be 76.8 kHz and the CLKOUT signal (when enabled) is 38.4 kHz clock output capable of driving other devices. 331 12.1.3 Functional Block Diagram S1-S7 7 S1-S7 S0 Receiver Control S0/IFIN IFIN Demodulator & Data Slicer Internal Control Unit EXTS0 EXTS1 SYMCLK Symbol Sync Noise Detector oDEC 76.8 kHz or 160 kHz Oscillator Sync Correlator TESTD External Control Unit RESET LOBAT CLKOUT Clock Generator De-interleaver Error Corrector Control/Status Registers Local Message Filter READY SPI Buffer SPI SPI Address Comparator/ Correlator 4 Figure 12-3 Block Diagram 332 12.2 SPI Packets All data communicated between the FLEX decoder and the host MCU is transmitted on the SPI in 32-bit packets. Each packet consists of an 8-bit ID followed by 24 bits of information. The FLEX decoder uses the SPI bus in full duplex mode. In other words, whenever a packet communication occurs, the data in both directions is valid packet data. The SPI interface consists of a READY pin and four SPI pins (SS, SCK, MOSI, and MISO).The SS is used as a chip select for the FLEX decoder. The SCK is a clock supplied by the host MCU. The data from the host is transmitted on the MOSI line. The data from the FLEX decoder is transmitted on the MISO line. Timing requirements for SPI communication are specified in 12.6.1, SPI Timing. 12.2.1 Packet Communication Initiated by the Host Refer to figure 12-4. When the host sends a packet to the FLEX decoder, it performs the following steps: 1. 2. 3. 4. 5. Select the FLEX decoder by driving the SS pin low. Wait for the FLEX decoder to drive the READY pin low. Send the 32-bit packet. De-select the FLEX decoder by driving the SS pin high. Repeat steps 1 through 4 for each additional packet. SS READY SCK MOSI MISO 1 2 3 D31 D31 4 D1 D0 D1 D0 D31 D31 D1 D0 D1 D0 D31 D31 D1 D0 D1 D0 High impedance state Figure 12-4 Typical Multiple Packet Communications Initiated by the Host When the host sends a packet, it will also receive a valid packet from the FLEX decoder. If the FLEX decoder is enabled (see 12.3.1, Checksum Packet for a definition of enabled) and has no other packets waiting to be sent, the FLEX decoder will send a status packet. 333 The host must transition the SS pin from high to low to begin each 32-bit packet. The FLEX decoder must see a negative transition on the SS pin in order for the host to initiate each packet communication. 12.2.2 Packet Communication Initiated by the FLEX decoder Refer to figure 12-5.When the FLEX decoder has a packet for the host to read, the following occurs: 1. The FLEX decoder drives the READY pin low. 2. If the FLEX decoder is not already selected, the host selects the FLEX decoder by driving the SS pin low. 3. The host receives (and sends) a 32-bit packet. 4. The host de-selects the FLEX decoder by driving the SS pin high (optional). SS READY SCK MOSI MISO 1 3 D31 D31 D1 D0 D1 D0 D31 D31 D1 D0 D1 D0 D31 D31 D1 D0 D1 D0 2 4 High impedance state Figure 12-5 Typical Multiple Packet Communications Initiated by the FLEX decoder When the host is reading a packet from the FLEX decoder, it must send a valid packet to the FLEX decoder. If the host has no data to send, it is suggested that the host send a Checksum Packet with all of the data bits set to 0 in order to avoid disabling the FLEX decoder. See 12.3.1, Checksum Packet for more details on enabling and disabling the FLEX decoder. The following figure illustrates that it is not necessary to de-select the FLEX decoder between packets when the packets are initiated by the FLEX decoder. 334 SS READY SCK MOSI MISO D31 D31 D1 D0 D1 D0 D31 D31 D1 D0 D1 D0 D31 D31 D1 D0 D1 D0 High impedance state Figure 12-6 Multiple Packet Communications Initiated by the FLEX decoder with No De-select 335 12.2.3 Host-to-Decoder Packet Map The upper 8 bits of a packet comprise the packet ID. The following table describes the packet ID's for all of the packets that can be sent to the FLEX decoder from the host. Table 12-1 Host-to-Decoder Packet ID Map Packet ID (Hexadecimal) 00 01 02 03 04 05 06 07 - 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C - 1F 20 21 22 23 24 336 Packet Type Checksum Configuration Control All Frame Mode Operator Message Address Enables Roaming Control Packet Timing Control Packet Reserved (Host should never send) Receiver Line Control Receiver Control Configuration (Off Setting) Receiver Control Configuration (Warm Up 1 Setting) Receiver Control Configuration (Warm Up 2 Setting) Receiver Control Configuration (Warm Up 3 Setting) Receiver Control Configuration (Warm Up 4 Setting) Receiver Control Configuration (Warm Up 5 Setting) Receiver Control Configuration (3200sps Sync Setting) Receiver Control Configuration (1600sps Sync Setting) Receiver Control Configuration (3200sps Data Setting) Receiver Control Configuration (1600sps Data Setting) Receiver Control Configuration (Shut Down 1 Setting) Receiver Control Configuration (Shut Down 2 Setting) Special (Ignored by FLEX decoder) Frame Assignment (Frames 112 through 127) Frame Assignment (Frames 96 through 111) Frame Assignment (Frames 80 through 95) Frame Assignment (Frames 64 through 79) Frame Assignment (Frames 48 through 63) Packet ID (Hexadecimal) 25 26 27 28 - 77 78 79 - 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 - FF Packet Type Frame Assignment (Frames 32 through 47) Frame Assignment (Frames 16 through 31) Frame Assignment (Frames 0 through 15) Reserved (Host should never send) User Address Enable Reserved (Host should never send) User Address Assignment (User address 0) User Address Assignment (User address 1) User Address Assignment (User address 2) User Address Assignment (User address 3) User Address Assignment (User address 4) User Address Assignment (User address 5) User Address Assignment (User address 6) User Address Assignment (User address 7) User Address Assignment (User address 8) User Address Assignment (User address 9) User Address Assignment (User address 10) User Address Assignment (User address 11) User Address Assignment (User address 12) User Address Assignment (User address 13) User Address Assignment (User address 14) User Address Assignment (User address 15) Reserved (Host should never send) 337 12.2.4 Decoder-to-Host Packet Map The following table describes the packet ID's for all of the packets that can be sent to the host from the FLEX decoder. Table 12-2 Decoder-to-Host Packet ID Map Packet ID (Hexadecimal) 00 01 02- 57 58 - 5F 60 61 - 7D 7E 7F 80 - FE FF Packet Type Block Information Word Address Vector or Message (ID is word number in frame) Reserved Roaming Status Packet Reserved Receiver Shutdown Status Reserved Part ID 12.3 Host-to-Decoder Packet Descriptions The following sections describe the packets of information sent from the host to the FLEX decoder. In all cases the packets should be sent MSB first (bit 7 of byte 3 = bit 31 of the packet = MSB). 12.3.1 Checksum Packet The Checksum Packet is used to insure proper communication between the host and the FLEX decoder. The FLEX decoder exclusive-or's the 24 data bits of every packet it receives (except the Checksum Packet and the special packet ID's 1C through 1F hexadecimal) with an internal checksum register. Upon reset and whenever the host writes a packet to the FLEX decoder, the FLEX decoder is disabled from sending any information to the host processor until the host processor sends a Checksum Packet with the proper checksum value (CV) to the FLEX decoder. When the FLEX decoder is disabled in this way, it prompts the host to read the Part ID Packet. Note that all other operation continues normally when the FLEX decoder is "disabled". Disabled only implies that data cannot be read, all other internal operations continue to function. When the FLEX decoder is reset, it is disabled and the internal checksum register is initialized to the 24 bit part ID defined in the Part ID Packet. See 12.4.8, Part ID Packet for a description of the Part ID. Every time a packet other than the Checksum Packet and the special packets 1C through 338 1F is sent to the decoder IC, the value sent in the 24 information bits is exclusive-or'ed with the internal checksum register, the result is stored back to the checksum register, and the FLEX decoder is disabled. If a Checksum Packet is sent and the CV bits match the bits in the checksum register, the FLEX decoder is enabled. If a Checksum Packet is sent when the FLEX decoder is already enabled, the packet is ignored by the FLEX decoder. If a packet other than the Checksum Packet is sent when the FLEX decoder is enabled, the decoder IC will be disabled until a Checksum Packet is sent with the correct CV bits. When the host reads a packet out of the FLEX decoder but has no data to send, the Checksum Packet should be sent so the FLEX decoder will not be disabled. The data in the Checksum Packet could be a null packet (32 bit stream of all zeros) since a Checksum Packet will not disable the FLEX decoder. When the host re-configures the FLEX decoder, the FLEX decoder will be disabled from sending any packets other than the Part ID Packet until the FLEX decoder is enabled with a Checksum Packet having the proper data. The ID of the Checksum Packet is 0. Table 12-3 Checksum Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 CV 23 CV 15 CV 7 Bit 6 0 CV 22 CV 14 CV 6 Bit 5 0 CV 21 CV 13 CV5 Bit 4 0 CV 20 CV 12 CV 4 Bit 3 0 CV 19 CV 11 CV 3 Bit 2 0 CV 18 CV 10 CV 2 Bit 1 0 CV 17 CV 9 CV 1 Bit 0 0 CV 16 CV 8 CV 0 CV: Checksum Value. 339 RESET Decoder disables itself Decoder initializes checksum register to Part ID value Decoder initiates Part ID Packet Decoder waits for SPI packet from host Yes Checksum Packet? No Yes Decoder disables itself Decoder enabled? No Decoder sets checksum register to the XOR of the packet data bits with the checksum register bits No Packet data matches checksum register data? Yes Decoder enables itself Figure 12-7 FLEX decoder Checksum Flow Chart 340 12.3.2 Configuration Packet The Configuration Packet defines a number of different configuration options for the FLEX decoder. Proper operation is not guaranteed if these settings are changed when decoding is enabled (i.e. the ON bit in the Control Packet is set). The ID of the Configuration Packet is 1. Table 12-4 Configuration Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 0 SME Bit 6 0 DFC 0 MOT Bit 5 0 0 0 COD Bit 4 0 0 0 MTE Bit 3 0 0 0 LBP Bit 2 0 IDE PCE ICO Bit 1 0 OFD1 SP1 0 Bit 0 1 OFD0 SP0 0 DFC: Disable Fractional Clock. When this bit is set and IDE is set, the CLKOUT signal will generate a 40 kHz signal (o DEC divided by 4). When this bit is cleared and IDE is set, the CLKOUT signal will generate 38.4 kHz signal (oDEC fractionally divided by 25/6 see diagram below). This bit has no effect when IDE is cleared. (value after reset=0) oDEC CLKOUT w/ DFC=1 CLKOUT w/ DFC=0 IDE: Internal Demodulator Enable. When this bit is set, the internal demodulator is enabled and the clock frequency at oDEC is expected to be 160 kHz. When this bit is cleared, the internal demodulator is disabled and the clock frequency at oDEC is expected to be 76.8 kHz. (value after reset=0) OFD: Oscillator Frequency Difference. These bits describe the maximum difference in the frequency of the 76.8 kHz oscillator crystal with respect to the frequency of the transmitter. These limits should be the worst case difference in frequency due to all conditions including but not limited to aging, temperature, and manufacturing tolerance. Using a smaller frequency difference in this packet will result in lower power consumption due to higher receiver battery save ratios. Note that this value is not the absolute error of the oscillator frequency provided to the FLEX decoder. The absolute error of the clock used by the FLEX transmitter must be taken into account. (e.g. If the transmitter tolerance is +/- 25 ppm and the oscillator tolerance is +/-140 ppm, the oscillator frequency difference is +/- 165 ppm and OFD should be set to 0.)(value after reset = 0) 341 OFD1 OFD0 0 0 1 1 0 1 0 1 Frequency Difference +/- 300 ppm +/- 150 ppm +/- 75 ppm +/- 0 ppm PCE: Partial Correlation Enable. When this bit is set, partial correlation of addresses is enabled. When partial correlation is enabled, the FLEX decoder will shutdown the receiver before the end of the last FLEX block which contains addresses if it can determine that none of the addresses in that FLEX block will match any enabled address in the FLEX decoder. When this bit is cleared, the receiver will be controlled as it was in previous versions of the FLEX decoder. (value after reset=0) SP: Signal Polarity. These bits set the polarity of EXTS1 and EXTS0 input signals. (value after reset=0) The polarity of the EXTS0 and EXTS1 bits will be determined by the receiver design. Signal Polarity SP1 SP0 0 0 1 1 0 1 0 1 EXTS1 Normal Normal Inverted Inverted EXTS0 Normal Inverted Normal Inverted FSK Modulation @ SP = 0,0 + 4800 Hz +1600 Hz - 1600 Hz - 4800 Hz EXTS1 1 1 0 0 EXTS0 0 1 1 0 SME: Synchronous Mode Enable. When this bit is set, a Status Packet will be automatically sent whenever the SMU (synchronous mode update) bit in the Status Packet is set. The host can use the SM (synchronous mode) bit in the Status Packet as an in-range/out-of-range indication. (value after reset=0) MOT: Maximum Off Time. This bit has no effect if AST in the Timing Control Packet is nonzero. When AST=0 and MOT=0, asynchronous A-word searches will time-out in 4 minutes. When AST=0 and MOT=1, asynchronous A-word searches will time-out in 1 minute. (value after reset=0) 342 COD: Clock Output Disable. When this bit is clear, a 38.4 kHz or 40 kHz (depending on the values of IDE and DFC) signal will be output on the CLKOUT pin. When this bit is set, the CLKOUT pin will be driven low. Note that setting and clearing this bit can cause pulses on the CLKOUT pin that are less than one half the clock period. Also note that when the clock output is enabled and not set for intermittent operation (see ICO in this packet), the CLKOUT pin will always output the clock signal even when the FLEX decoder is in reset (as long as the FLEX decoder oscillator is seeing clocks). Further note that when the FLEX decoder is used in internal demodulator mode (i.e. uses a 160 kHz oscillator), the CLKOUT pin will be 80 kHz from reset until the time the IDE bit is set. This is because the FLEX decoder defaults to external demodulator mode at reset. (value after reset=0) MTE: Minute Timer Enable. When this bit is set, a Status Packet will be sent at one minute intervals with the MT (minute time-out) bit in the Status Packet set. When this bit is clear, the internal one-minute timer stops counting. The internal one-minute timer is reset when this bit is changed from 0 to 1 or when the MTC (minute timer clear) bit in the Control Packet is set. Note that the minute timer will not be accurate using a 160 kHz oscillator until the IDE bit is set. (value after reset=0) LBP: Low Battery Polarity. This bit defines the polarity of the FLEX decoder's LOBAT pin. The LB bit in the Status Packet is initialized to the inverse value of this bit when the FLEX decoder is turned on (by setting the ON bit in the Control Packet). When the FLEX decoder is turned on, the first low battery update in the Status Packet will be sent to the host when a low battery condition is detected on the LOBAT pin. Setting this bit means that a high on the LOBAT pin indicates a low voltage condition. (value after reset=0) ICO: Intermittent Clock Out. When this bit is clear and COD is clear, a 38.4 kHz or 40 kHz (depending on the values of IDE and DFC) signal will be output on the CLKOUT pin. When this bit is set and COD is clear, the clock will only be output on the CLKOUT pin while the receiver is not in the Off state. The clock will be output for a few cycles before the receiver transitions from the off state and for a few cycles after the receiver transitions to the off state (this is to insure that the receiver receives enough clocks to detect and process the changes to and from the Off state). The CLKOUT pin will be driven low when it is not driving a clock. Note that when the clock is automatically enabled and disabled (i.e. when ICO is set), the CLKOUT signal transitions will be clean (i.e. no pulses less than half the clock period) when it transitions between no clock and clocked output. This bit has no effect when COD is set. (value after reset=0) 343 12.3.3 Control Packet The Control Packet defines a number of different control bits for the FLEX decoder. The ID of the Control Packet is 2. Table 12-5 Control Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 FF7 0 0 Bit 6 0 FF6 SPM SBI Bit 5 0 FF5 PS1 0 Bit 4 0 FF4 PS0 MTC Bit 3 0 FF3 0 0 Bit 2 0 FF2 0 0 Bit 1 1 FF1 0 EAE Bit 0 0 FF0 0 ON FF: Force Frame 0-7. These bits enable and disable forcing the FLEX decoder to look in frames 0 through 7. When an FF bit is set, the FLEX decoder will decode the corresponding frame. Unlike the AF bits in the Frame Assignment Packets, the system collapse of a FLEX system will not affect frames assigned using the FF bits (e.g. Where as setting AF 0 to 1 when the system collapse is 5 will cause the decoder to decode frames 0, 32, 64, and 96, setting FF0 to 1 when the system collapse is 5 will only cause the decoder to decode frame 0.). This may be useful for acquiring transmitted time information or channel attributes (e.g. Local ID). (value after reset=0) SPM: Single Phase Mode. When this bit is set, the FLEX decoder will decode only one phase of the transmitted data. When this bit is clear, the FLEX decoder will decode all of the phases it receives. A change to this bit while the FLEX decoder is on, will not take affect until the next block 0 of the next decoded frame. (value after reset=0) PS: Phase Select. When the SPM bit is set, these bits define what phase the FLEX decoder should decode according to the following table. This value is determined by the service provider. A change to these bits while the FLEX decoder is on, will not take affect until the next block 0 of a frame. (value after reset=0) PS Value PS1 0 0 1 1 PS0 0 1 0 1 Phase Decoded (based on FLEX Data Rate) 1600bps a a a a 3200bps a a c c 6400bps a b c d SBI: Send Block Information words 2-4. When this bit is set, any errored or time related block information words 2-4 will be sent to the host. See 12.4.1, Block Information Word Packet for a description of the words sent. (value after reset=0) 344 MTC: Minute Timer Clear. Setting this bit will cause the one minute timer to restart from 0. EAE: End of Addresses Enable. When this bit is set, the EA bit in the Status Packet will be set immediately after the FLEX decoder decodes the last address word in the frame if any of the enabled FLEX decoder addresses was detected in the frame. When this bit is cleared, the EA bit will never be set. ON: Turn On Decoder. Set if the FLEX decoder should be decoding FLEX signals. Clear if signal processing should be off (very low power mode). If the ON bit is changed twice and the control packets making the changes are received within 2ms of each other, the FLEX decoder may ignore the double change and stay in its original state (e.g. if it is turned off then on again within 2ms it may stay on and ignore the off pulse). Therefore it is recommended that the host insures a minimum of 2ms between changes in the ON bit. (value after reset=0) Note: Turning off the FLEX decoder must be done using the following sequence. This sequence is performed automatically by the FLEXstack software version 1.2 and greater. 1. Turn off the FLEX decoder by sending a Control Packer with the ON bit cleared. 2. Turn on the FLEX decoder by sending a Control Packer with the ON bit set. 3. Turn off the FLEX decoder by sending a Control Packer with the ON bit cleared. Timing between these steps is specified below and is measured from the positive edge of the last clock of one packet to the positive edge of the last clock of the next packet: * The minimum time between steps 1 and 2 is 2ms or the programmed shut down time, whichever is greater. The programmed shut down time is the sum of all the of the times programmed in the used Receiver Shut Down Settings Packets. * There is no maximum time between steps 1 and 2. * The minimum time between steps 2 and 3 is 2ms. * The maximum time between steps 2 and 3 is the programmed warm up time minus 2ms. The programmed warm up time is the sum of all the of the times programmed in the used Receiver Warm Up Settings Packets. 12.3.4 All Frame Mode Packet The All Frame Mode Packet is used to decrement temporary address enable counters by one, decrement the all frame mode counter by one, and/or enable or disable forcing all frame mode. All frame mode is enabled if any temporary address enable counter is non-zero, the all frame mode counter is non-zero, or the force all frame mode bit is set. If all frame mode is enabled, the FLEX decoder will attempt to decode every frame and send a Status Packet with the EOF (end-of-frame) bit set at the end of every frame. Both the all frame mode counter and the temporary address enable counters can only be incremented internally by the FLEX decoder and can only be decremented by the host. The FLEX decoder will increment a temporary address enable counter whenever a short instruction vector is received assigning the corresponding temporary address. 345 See 12.5.4, Operation of a Temporary Address for details. The FLEX decoder will increment the all frame mode counter whenever an alphanumeric, HEX / binary, or secure vector is received. When the host determines that a message associated with a temporary address, or a fragmented message has ended, then the appropriate temporary address counter or all frame mode counter should be decremented by writing an All Frame Mode Packet to the FLEX decoder in order to exit the all frame mode, thereby improving battery life. See 12.5.3, Building a Fragmented Message for details. Neither the temporary address enable counters nor the all frame mode counter can be incremented past the value 127 (i.e. it will not roll-over) or decremented past the value 0. The temporary address enable counters and the all frame mode counter are initialized to 0 at reset and when the decoder is turned off. The ID of the All Frame Mode Packet is 3. Table 12-6 All Frame Mode Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 DAF DTA15 DTA7 Bit 6 0 FAF DTA 14 DTA 6 Bit 5 0 0 DTA 13 DTA 5 Bit 4 0 0 DTA12 DTA 4 Bit 3 0 0 DTA11 DTA 3 Bit 2 0 0 DTA10 DTA 2 Bit 1 1 0 DTA9 DTA 1 Bit 0 1 0 DTA 8 DTA 0 DAF: Decrement All Frame counter. Setting this bit decrements the all frame mode counter by one. If a packet is sent with this bit clear, the all frame mode counter is not affected. (value after reset =0) FAF: Force All Frame mode. Setting this bit forces the FLEX decoder to enter all frame mode. If this bit is clear, the FLEX decoder may or may not be in all frame mode depending on the status of the all frame mode counter and the temporary address enable counters. This may be useful in acquiring transmitted time information. (value after reset=0) DTA: Decrement Temporary Address enable counter. When a bit in this word is set, the corresponding temporary address enable counter is decremented by one. When a bit is cleared, the corresponding temporary address enable counter is not affected. When a temporary address enable counter reaches zero, the temporary address is disabled.(value after reset=0) 346 12.3.5 Operator Messaging Address Enable Packet The contents of this section apply to the FLEXTM Roaming Decoder. They are not applicable to the FLEXTM Non-Roaming Decoder. The operator messaging address enable packet is used to enable and disable the built-in FLEX operator messaging addresses. Enabling and disabling operator messaging addresses does not affect what frames the decoder IC decodes. To decode the proper frames, the host must modify the FF bits in the Control Packet or the AF bits in the Frame Assignment Packets. The ID of the operator messaging address enable packet is 4. Table 12-7 System Address Enable Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 OAE15 OAE 7 Bit 6 0 0 OAE 14 OAE 6 Bit 5 0 0 OAE 13 OAE 5 Bit 4 0 0 OAE 12 OAE 4 Bit 3 0 0 OAE 11 OAE 3 Bit 2 1 0 OAE 10 OAE 2 Bit 1 0 0 OAE 9 OAE 1 Bit 0 0 0 OAE 8 OAE 0 OAE: Operator messaging Address Enable. When a bit is set, the corresponding operator messaging address is enabled. When it is cleared, the corresponding operator messaging address is disabled. OAE0 through OAE 15 corresponds to the hexadecimal operator messaging address values of 1F7810 through 1F781F respectively. (value after reset=0) 12.3.6 Roaming Control Packet The contents of this section apply to the FLEXTM Roaming Decoder. They are not applicable to the FLEXTM Non-Roaming Decoder. The roaming control packet controls the features of the FLEX decoder that allow implementation of a roaming device. The ID of the roaming control packet is 5. Table 12-8 Roaming Control Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 IRS RND 0 Bit 6 0 NBC ABI 0 Bit 5 0 MCM SAS MFC1 Bit 4 0 IS1 DAS MFC0 Bit 3 0 SDF 0 0 Bit 2 1 RSP 0 0 Bit 1 0 SND 0 MCO1 Bit 0 1 CND 0 MCO0 347 IRS: Ignore Re-synchronization Signal. When this bit is set, the FLEX decoder will not go asynchronous when detecting an Ar or Ar signal during searches for A-words. It will merely report that the re-synchronization signal was received by setting RSR to 1 in the Roaming Status packet. This allows the host to decide what to do when the paging device is synchronous to more than one channel and only one channel is sending the re-synchronization signal. It also prevents the FLEX decoder from losing synchronization when it detects the re-synchronization signal while the paging device is checking an unknown channel. This bit is set and cleared by the host. (value after reset=0) NBC: Network Bit Check. Setting this bit will enable reporting of the received network bit value (NBU and n) in the Roaming Status Packet. Setting this bit also makes the FLEX decoder abandon a frame after the Frame Info word without synchronizing to the frame if the frame information word is uncorrectable or if the n bit in the frame information word is not set. If the FLEX decoder was in synchronous mode when this occurred (probably due to synchronizing to a second channel), it will maintain synchronization to the original channel. If the FLEX decoder was in asynchronous mode when this occurred, it will stay in asynchronous mode and end the A-word search. This is done to avoid synchronizing to a non-roaming channel when searching for roaming channels. This bit is set and cleared by the host. (value after reset=0) MCM: Manual Collapse Mode. When this bit is set, the FLEX decoder behaves as if the system collapse was 7. The FLEX decoder will not apply the received system collapse to the AF bits. When this bit is set, the received system collapse is reported to the host via SCU and RSC in the Roaming Status Packet. This is so the host can modify the AF bits based on the system collapse of the channel. This bit is set and cleared by the host. (value after reset=0) IS1:Invert EXTS1. Setting this bit inverts the expected polarity of the EXTS1 pin from the way it is configured by SP 1 in the Configuration Packet (e.g. if both IS1 and SP 1 are set, the polarity of the EXTS1 pin is untouched). This bit is intended to be changed when a change in a channel changes the polarity of the received signal. This bit is set and cleared by the host. This bit has the equivalent effect when using the internal demodulator. (value after reset=0) SDF: Stop Decoding Frame. Setting this bit causes the FLEX decoder to stop decoding a frame without losing frame synchronization. This bit is set by the host, and cleared by the FLEX decoder once it has been processed. The packet with the SDF bit set must be sent after receiving the status packet with EA bit set. It must be sent within 40ms of the end of block in which the FLEX decoder set the EA bit. (value after reset=0) RSP: Receiver Shutdown Packet enable. When this bit is set, a Receiver Shutdown Packet will be sent whenever the receiver is shut down. The receiver shutdown packet informs the host that the receiver shutdown, and how long it will be before the FLEX decoder will automatically warm the receiver back up. (value after reset=0) SND: Start Noise Detect. Setting this bit while the FLEX decoder is battery saving will cause it to warm-up the receiver, run a noise detect, and report the result of the noise detect via NDR in the 348 Roaming Status Packet. This bit is set by the host, and cleared by the FLEX decoder once it has been processed. If the time comes for the FLEX decoder to warm up automatically or the SAS bit is set while an SND is being processed, the noise detect will be abandoned and the abandoned noise detect result (NDR = 01) will be sent in the Roaming Status Packet. (value after reset=0) CND: Continuous Noise Detect. Setting this bit will cause the FLEX decoder to do continuous noise detects during the decoded block data of a frame. The results of the noise detect will only be reported if noise is detected (NDR = 11). Only one noise detected result (NDR=11) will be sent per block. If the FLEX decoder has not completed a noise detect when it shuts down for the frame, that noise detect will be abandoned, but no abandon result (NDR=01) will be sent. This bit is set and cleared by the host. (value after reset=0) RND: Report Noise Detects. Setting this bit will cause the FLEX decoder to report the results of the noise detects it does under normal asynchronous operation (when first turned on and when asynchronous). The results of the noise detect will be reported via NDR in the Roaming Status Packet. This bit is set and cleared by the host. (value after reset=0) ABI: All Block Information words. When this bit is set, the FLEX decoder will send all received Block Information words 2-4 to the host. Note: Setting the SBI bit in the Control Packet only enables errored and real time clock related block info words. (value after reset=0) SAS: Start A-word Search. Setting this bit while in asynchronous battery save mode will cause the FLEX decoder to warm-up the receiver and run an A-word search. If, during the A-word search, the FLEX decoder finds sufficient FLEX signal, it will enter synchronous mode and start decoding the frame. If the A-word search times-out without finding sufficient FLEX signal, it will battery save and continue doing periodic noise detects. The time-out for the A-word searches is controlled by the AST bits in the Timing Control Packet and the MOT bit in the Configuration Packet. The A-word search takes priority over noise detects. Therefore, if the FLEX decoder is performing an A-word search and the time comes to do automatic noise detect, the noise detect will not be performed. This bit is set by the host, and cleared by the FLEX decoder once it has been acted on. (value after reset=0) DAS: Disable A-word Search. When this bit is set, an A-word search will not automatically occur after a noise detect in asynchronous mode finds FLEX signal. This includes automatic noise detects and noise detects initiated by the host by setting SND. The FLEX decoder will shut down the receiver after the noise detect completes regardless of the result. When this bit is cleared, Aword searches will occur after a noise detect finds signal in asynchronous mode. (value after reset=0) MFC: Missed Frame Control. These bits control the frames for which missing frame data (MS1, MFI, MS2, MBI, and MAW) is reported in the Roaming Status Packet. (value after reset=0) 349 MFC1 MFC0 0 0 1 1 0 1 0 1 Missing Frame Data Reported Never Only during frames 0 through 3 Only during frames 0 through 7 Always MCO: Maximum Carry On. The value of these bits sets the maximum carry on that the FLEX decoder will follow. For example, if the FLEX decoder receives a carry on of 3 over the air and MCO is set to 1, the FLEX decoder will only carry on for one frame. (value after reset=3) 12.3.7 Timing Control Packet The contents of this section apply to the FLEXTM Roaming Decoder. They are not applicable to the FLEXTM Non-Roaming Decoder. The timing control packet gives the host control of the timing used when the FLEX decoder is in asynchronous mode. The packet ID for the timing control packet is 6. Table 12-9 Timing Control Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 AST 7 ABT 7 Bit 6 0 0 AST 6 ABT 6 Bit 5 0 0 AST 5 ABT 5 Bit 4 0 0 AST 4 ABT 4 Bit 3 1 0 AST 3 ABT 3 Bit 2 1 0 AST 2 ABT 2 Bit 1 1 0 AST 1 ABT 1 Bit 0 1 0 AST 0 ABT 0 AST: A-word Search Time. The value of these bits sets the A-word search time for all asynchronous A-word searches in units of 80ms (e.g. value of 1 is 80ms, value of 2 is 160ms, etc.) If the value is 0, the FLEX decoder defaults to the 1-minute (MOT=1) or 4-minute (MOT=0) Aword search time controlled by the MOT bit in the configuration packet. (Value after reset=0) ABT: Asynchronous Battery-save Time. The value of these bits sets the battery save time (time from the beginning of one automatic noise detect to the beginning of the next automatic noise detect) in asynchronous mode in units of 80ms (e.g. value of 1 is 80ms, value of 2 is 160ms, etc.) If the value is 0, the battery save time is set to the default value of 1.5 seconds. The minimum allowed ABT is 320ms, therefore values of 1, 2, 3, and 4 are invalid. (Value after reset=0) 350 12.3.8 Receiver Line Control Packet This packet gives the host control over the settings on the receiver control lines (S0-S7) in all modes except reset. In reset, the receiver control lines are in high impedance settings. The ID for the Receiver Line Control Packet is 15 (decimal). Table 12-10 Receiver Line Control Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 FRS 7 CLS 7 Bit 6 0 0 FRS 6 CLS 6 Bit 5 0 0 FRS 5 CLS 5 Bit 4 0 0 FRS 4 CLS 4 Bit 3 1 0 FRS 3 CLS 3 Bit 2 1 0 FRS 2 CLS 2 Bit 1 1 0 FRS 1 CLS 1 Bit 0 1 0 FRS 0 CLS 0 FRS: Force Receiver Setting. Setting a bit to one will cause the corresponding CLS bit in this packet to override the internal receiver control settings on the corresponding receiver control line (S0-S7). Clearing a bit gives control of the corresponding receiver control lines (S0-S7) back to the FLEX decoder.(value after reset=0) CLS: Control Line Setting. If the corresponding FRS bit was set in this packet, these bits define what setting should be applied to the corresponding receiver control lines.(value after reset=0) 12.3.9 Receiver Control Configuration Packets These packets allow the host to configure what setting is applied to the receiver control lines S0S7, how long to apply the setting, and when to read the value of the LOBAT input pin. For a more detailed description of how the FLEX decoder uses these settings see 12.5.1, Receiver Control. The FLEX decoder defines 12 different receiver control settings. Proper operation is not guaranteed if these settings are changed when decoding is enabled (i.e. the ON bit in the Control Packet is set). The IDs for these packets range from 16 to 27 (decimal). 1. Receiver Off Setting Packet Table 12-11 Receiver Off Setting Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 CLS 7 ST 7 Bit 6 0 0 CLS 6 ST 6 Bit 5 0 0 CLS 5 ST 5 Bit 4 1 0 CLS 4 ST 4 Bit 3 0 LBC CLS 3 ST 3 Bit 2 0 0 CLS 2 ST 2 Bit 1 0 0 CLS 1 ST 1 Bit 0 0 0 CLS 0 ST 0 351 LBC: Low Battery Check. If this bit is set, the FLEX decoder will check the status of the LOBAT port just before leaving this receiver state. (value after reset=0) CLS: Control Line Setting. This is the value to be output on the receiver control lines (S0-S7) for this receiver state. (value after reset=0) ST: Step Time. This is the time the FLEX decoder is to keep the receiver off before applying the first warm up state's receiver control value to the receiver control lines. The setting is in steps of 625s. Valid values are 625s (ST=01) to 159.375ms (ST=FF in hexadecimal). (value after reset=625s) 2. Receiver Warm Up Setting Packets Table 12-12 Receiver Warm Up Setting Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 SE CLS 7 0 Bit 6 0 0 CLS 6 ST 6 Bit 5 0 0 CLS 5 ST 5 Bit 4 1 0 CLS 4 ST 4 Bit 3 0 LBC CLS 3 ST 3 Bit 2 s2 0 CLS 2 ST 2 Bit 1 s1 0 CLS 1 ST 1 Bit 0 s0 0 CLS 0 ST 0 s: Setting Number. Receiver control setting for which this packet's values are to be applied. The following truth table shows the names of each of the values for s that apply to this packet. s2 0 0 0 1 1 s1 0 1 1 0 0 s0 1 0 1 0 1 Setting Name Warm Up 1 Warm Up 2 Warm Up 3 Warm Up 4 Warm Up 5 SE: Step Enable. The receiver setting is enabled when the bit is set. If a step in the warm up sequence is disabled, the disabled step and all remaining steps will be skipped. (value after reset=0) LBC: Low Battery Check. If this bit is set, the FLEX decoder will check the status of the LOBAT port just before leaving this receiver state. (value after reset=0) CLS: Control Line Setting. This is the value to be output on the receiver control lines (S0-S7) for this receiver state. (value after reset=0) 352 ST: Step Time. This is the time the FLEX decoder is to wait before applying the next state's receiver control value to the receiver control lines. The setting is in steps of 625s. Valid values are 625s (ST=01) to 79.375ms (ST=7F in hexadecimal). (value after reset=625s) 3. 3200sps Sync Setting Packets Table 12-13 3200sps Sync Setting Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 CLS 7 0 Bit 6 0 0 CLS 6 ST 6 Bit 5 0 0 CLS 5 ST 5 Bit 4 1 0 CLS 4 ST 4 Bit 3 0 LBC CLS 3 ST 3 Bit 2 1 0 CLS 2 ST 2 Bit 1 1 0 CLS 1 ST 1 Bit 0 0 0 CLS 0 ST 0 LBC: Low Battery Check. If this bit is set, the FLEX decoder will check the status of the LOBAT port just before leaving this receiver state. (value after reset=0) CLS: Control Line Setting. This is the value to be output on the receiver control lines (S0-S7) for this receiver state. (value after reset=0) ST: Step Time. This is the time the FLEX decoder is to wait before expecting good signals on the EXTS1 and EXTS0 signals after warming up. The setting is in steps of 625s. Valid values are 625s (ST=01) to 79.375ms (ST=7F in hexadecimal). (value after reset=625s) 4. Receiver On Setting Packets Table 12-14 Receiver On Setting Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 CLS 7 0 Bit 6 0 0 CLS 6 0 Bit 5 0 0 CLS 5 0 Bit 4 1 0 CLS 4 0 Bit 3 s3 LBC CLS 3 0 Bit 2 s2 0 CLS 2 0 Bit 1 s1 0 CLS 1 0 Bit 0 s0 0 CLS 0 0 353 s: Setting Number. Receiver control setting for which this packet's values are to be applied. The following truth table shows the names of each of the values for s that apply to this packet. s3 s2 s1 s0 0111 1000 1001 Setting Name 1600sps Sync 3200sps Data 1600sps Data LBC: Low Battery Check. If this bit is set, the FLEX decoder will check the status of the LOBAT port just before leaving this receiver state. (value after reset=0) CLS: Control Line Setting. This is the value to be output on the receiver control lines (S0-S7) for this receiver state. (value after reset=0) 5. Receiver Shut Down Setting Packets Table 12-15 Receiver Shut Down Setting Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 SE CLS 7 0 Bit 6 0 0 CLS 6 0 Bit 5 0 0 CLS 5 ST 5 Bit 4 1 0 CLS 4 ST 4 Bit 3 1 LBC CLS 3 ST 3 Bit 2 0 0 CLS 2 ST 2 Bit 1 1 0 CLS 1 ST 1 Bit 0 s 0 CLS 0 ST 0 s: Setting Number. Receiver control setting for which this packet's values are to be applied. The following truth table shows the names of each of the values for s that apply to this packet. s 0 1 Setting Name Shut Down 1 Shut Down 2 SE: Step Enable. The receiver setting is enabled when the bit is set. If a step in the shut down sequence is disabled, all steps following the disabled step will be ignored. (value after reset=0) LBC: Low Battery Check. If this bit is set, the FLEX decoder will check the status of the LOBAT port just before leaving this receiver state. (value after reset=0) CLS: Control Line Setting. This is the value to be output on the receiver control lines (S0-S7) for this receiver state. (value after reset=0) 354 ST: Step Time. This is the time the FLEX decoder is to wait before applying the next state's receiver control value to the receiver control lines. The setting is in steps of 625s. Valid values are 625s (ST=01) to 39.375ms (ST=3F in hexadecimal). (value after reset=625s) 12.3.10 Frame Assignment Packets The FLEX protocol defines that each address of a FLEX pager is assigned a home frame and a battery cycle. The FLEX decoder must be configured so that a frame that is assigned by one or more of the addresses' home frames and battery cycles has its corresponding configuration bit set. For example, if the FLEX decoder has one enabled address and it is assigned to frame 3 with a battery cycle of 4, the AF bits for frames 3, 19, 35, 51, 67, 83, 99, and 115 should be set and the AF bits for all other frames should be cleared. When the FLEX decoder is configured for manual collapse mode by setting the MCM bit in the Roaming Control Packet, the FLEX decoder will not apply the received system collapse to the AF bits. The host should set the AF bits for all frames that should be decoded on all channels. For example, if frames 0 and 64 should be decoded on one channel and frames 4, 36, 68, and 100 should be decoded on another channel, all six of the corresponding AF bits should be set. The host can then change the receiver's carrier frequency after the FLEX decoder decodes frames 0, 36, 64, and 100. There are 8 Frame Assignment Packets. The Packet IDs for these packets range from 32 to 39 (decimal). Table 12-16 Frame Assignment Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 AF 15 AF 7 Bit 6 0 0 AF 14 AF 6 Bit 5 1 0 AF 13 AF 5 Bit 4 0 0 AF 12 AF 4 Bit 3 0 0 AF 11 AF 3 Bit 2 f2 0 AF 10 AF 2 Bit 1 f1 0 AF 9 AF 1 Bit 0 f0 0 AF 8 AF 0 f: Frame range. This value determines which 16 frames correspond to the 16 AF bits in the packet according to the following table. At least one of these bits must be set when the FLEX decoder is turned on by setting the ON bit in the control packet. (value after reset=0) 355 f2 f1 f0 000 001 010 011 100 101 110 111 AF15 Frame 127 Frame 111 Frame 95 Frame 79 Frame 63 Frame 47 Frame 31 Frame 15 AF0 Frame 112 Frame 96 Frame 80 Frame 64 Frame 48 Frame 32 Frame 16 Frame 0 AF: Assigned Frame. If a bit is set, the FLEX decoder will consider the corresponding frame to be assigned via an address's home frame and pager collapse. (value after reset=0) 12.3.11 User Address Enable Packet The User Address Enable Packet is used to enable and disable the 16 user address words. Although the host is allowed to change the user address words while the FLEX decoder is decoding FLEX signals, the host must disable a user address word before changing it. The ID of the User Address Enable Packet is 120 (decimal). Table 12-17 User Address Enable Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 UAE 15 UAE 7 Bit 6 1 0 UAE 14 UAE 6 Bit 5 1 0 UAE 13 UAE 5 Bit 4 1 0 UAE 12 UAE 4 Bit 3 1 0 UAE 11 UAE 3 Bit 2 0 0 UAE 10 UAE 2 Bit 1 0 0 UAE 9 UAE 1 Bit 0 0 0 UAE 8 UAE 0 UAE: User Address Enable. When a bit is set, the corresponding user address word is enabled. When it is cleared, the corresponding user address word is disabled. UAE0 corresponds to the user address word configured using a packet ID of 128, and UAE15 corresponds to the user address word configured using a packet ID of 143. (value after reset=0) 356 12.3.12 User Address Assignment Packets The FLEX decoder has 16 user address words. Each word can be programmed to be a short address, part of a long address, or the first part of a network ID. The addresses are configured using the Address Assignment Packets. Each user address can be configured as long or short and tone-only or regular (network ID's are short and regular). Although the host is allowed to send these packets while the FLEX decoder is on, the host must disable the user address word by clearing the corresponding UAE bit in the User Address Enable Packet before changing any of the bits in the corresponding User Address Assignment Packet. This method allows for easy reprogramming of user addresses without disrupting normal operation. The IDs for these packets range from 128 to 143 (decimal). Table 12-18 User Address Assignment Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 1 0 A15 A7 Bit 6 0 LA A 14 A6 Bit 5 0 TOA A13 A5 Bit 4 0 A20 A12 A4 Bit 3 a3 A19 A 11 A3 Bit 2 a2 A18 A 10 A2 Bit 1 a1 A17 A9 A1 Bit 0 a0 A16 A8 A0 a: User Address Word Number. This specifies which address word is being configured. A zero in this field corresponds to address index zero (AI = 0) in the Address Packet received from the FLEX decoder when an address is detected. See 12.4.2, Address Packet for a description of the address index field. LA: Long address. When this bit is set, the address is considered a long address. Both words of a long address must have this bit set. The first word of a long address must have an even address index and the second word must be in the address index immediately following the first word. TOA: Tone-Only Address. When this bit is set, the FLEX decoder will consider this address a tone-only address and will not decode a vector word when the address is received. If the TOA bit of a long address word is set, the TOA bit of the other word of the long address must also be set. A: Address word. This is the 21 bit value of the address word. Valid FLEX messaging addresses or Network ID's may be used. 357 12.4 Decoder-to-Host Packet Descriptions The following sections describe the packets of information that will be sent from the FLEX decoder to the host. In all cases the packets are sent MSB first (bit 7 of byte 3 = bit 31 of the packet = MSB). The FLEX decoder decides what data should be sent to the host. If the FLEX decoder is disabled through the checksum feature (see 12.3.1, Checksum Packet for a description of the checksum feature) the Part ID Packet will be sent. Data Packets relating to data received over the air are buffered in the 32 packet transmit buffer. The Data packets include Block Information Word Packets, Address Packets, Vector Packets, and Message Packets. If the FLEX decoder is enabled and a receiver shutdown packet is pending, the receiver shutdown packet will be sent. If there is no receiver shutdown packet pending, but there is a roaming status packet pending, the roaming status packet will be sent. If neither the receiver shutdown packet nor the roaming status packet is pending and there is data in the transmit buffer, a packet from the transmit buffer will be sent. Otherwise, the FLEX decoder will send the Status Packet (which is not buffered). In the event of a buffer overflow, the FLEX decoder will automatically stop decoding and clear the buffer. It is recommended that the Host be designed to empty the FIFO buffer every block with enough time left over to read a status packet. This would ensure that any applicable Status Packet would be received within 1 block of the new status being available. 32 32 32 Part ID Register Receiver Shutdown Register Roaming Status Register MUX 32 SPI Transmit Register MISO 32x32 Data Packet FIFO Transmit Buffer 32 Status Register 32 Figure 12-8 FLEX decoder SPI Transmit Functional Block Diagram 358 12.4.1 Block Information Word Packet The Block Information Field is the first field following the synchronization codes of the FLEX protocol. This field contains information about the frame such as number of addresses and messages, information about current time, the channel ID, channel attributes, etc. The first block information word of each phase is used internally to the FLEX decoder and is never transmitted to the host with the exception of the system collapse which is sent to the host when the FLEX decoder is in manual collapse mode. Time block information words 2-4 can be optionally sent to the host by setting the SBI bit in the control packet (see 12.3.3, Control Packet). All block information words 2-4 can be optionally sent to the host by setting the ABI bit in the roaming control packet. When the SBI or ABI bit is set and any block information word 2-4 is received with an uncorrectable number of biterrors, the FLEX decoder will send the block information word to the host with the e bit setregardless of the value of the f field in the block information word. The FLEX decoder does not support decoding of the vector and message words associated with the Data/System Message block info word (f=101). The ID of a Block Information Word Packet is 0 (decimal). Table 12-19 Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 e x s7 Block Information Word Packet Bit Assignments Bit 6 0 p1 x s6 Bit 5 1 p0 s 13 s5 Bit 4 0 x s 12 s4 Bit 3 0 x s 11 s3 Bit 2 0 f2 s 10 s2 Bit 1 0 f1 s9 s1 Bit 0 0 f0 s8 s0 e: Set if more than 2 bit errors are detected in the word or if the check character calculation fails after error correction has been performed. p: Phase on which the block information word was found (0=a, 1=b, 2=c, 3=d) x: Unused bits. The value of these bits is not guaranteed. f: Word Format Type. The value of these bits modify the meaning of the s bits in this packet as described in the BIW word descriptions in the s bit definition below. s: These are the information bits of the block information word. The definition of these bits depend on the f bits in this packet. The following table describes the block information words. 359 f2 0 0 0 0 1 1 1 1 f1 0 0 1 1 0 0 1 1 f0 1 s13 s12 s11 s10 s9 i7 i6 i5 i4 s8 i3 d3 s7 i2 d2 s6 i1 d1 s5 i0 d0 s4 s3 s2 s1 s0 Description 0* i8 C4 C3 C2 C1 C0 Local ID, Coverage Zone Y4 Y3 Y2 Y1 Y0 Month, Day, Year 1* 2 m3 m2 m1 m0 d4 0* S2 S1 1 2 S0 M5 M4 M3 M2 M1 M0 H4 H3 H2 H1 H0 Second, Minute, Hour 1* Reserved by FLEX protocol for future use 0* 1 Reserved by FLEX protocol for future use 1* 2 z 9 1 z8 z7 z6 z5 z4 z3 z2 z1 z0 A3 A2 A1 A0 System Message 0* Reserved by FLEX protocol for future use 1* 1 c 9 c8 c7 c6 c5 c4 c3 c2 c1 c0 T3 T2 T1 T0 Country Code, Traffic Management Flags Notes: 1. Will be decoded only if the ABI bit is set. 2. Will be decoded only if the SBI or ABI bit is set. 12.4.2 Address Packet The Address Field follows the Block Information Field in the FLEX protocol. It contains all of the addresses in the frame. If less than three bit errors are detected in a received address word and it matches an enabled address assigned to the FLEX decoder, an Address Packet will be sent to the host processor. The Address Packet contains assorted data about the address and its associated vector and message. The ID of an Address Packet is 1 (decimal). Table 12-20 Address Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 PA AI 7 TOA Bit 6 0 p1 AI 6 WN 6 Bit 5 0 p0 AI 5 WN 5 Bit 4 0 LA AI 4 WN 4 Bit 3 0 x AI 3 WN 3 Bit 2 0 x AI 2 WN 2 Bit 1 0 x AI 1 WN 1 Bit 0 1 x AI 0 WN 0 PA: Priority Address. Set if the address was received as a priority address. p: Phase on which the address was detected (0=a, 1=b, 2=c, 3=d) LA: Long Address type. Set if the address was programmed in the FLEX decoder as a long address. AI: Address Index (valid values are 0 through 15 and 128 through 159). The index identifies which of the addresses was detected. Values 0 through 15 correspond to the 16 programmable 360 address words. Values 128 through 143 correspond to the 16 temporary addresses. Values 144 through 159 correspond to the 16 operator messaging addresses. For long addresses, the address detect packet will only be sent once and the index will refer to the second word of the address. TOA: Tone Only Address. Set if the address was programmed in the FLEX decoder as a toneonly address. This bit will never be set for temporary or operator messaging addresses. No vector word will be sent for tone-only addresses. WN: Word number of vector (2 - 87). Describes the location in the frame of the vector word for the detected address. This value is invalid for this packet if the TOA bit is set. x: Unused bits. The value of these bits is not guaranteed. 12.4.3 Vector Packet The Vector Field follows the Address Field in the FLEX protocol. Each Vector Packet must be matched to its corresponding Address Packet. The ID of the vector packet is the word number where the vector word was received in the frame. This value corresponds to the WN bits sent in the associated address packet. The phase information in both the Address Packet and the Vector Packet must also match. It is important to note for long addresses, the first message word will be transmitted in the word location immediately following the associated vector. See12.5.2, Message Building for a message building example. In this case, the word number (identified by b6 to b0 ) in the Vector Packet will indicate the message start of the second message word if the message is longer than 1 word. There are several types of vectors - 3 types of Numeric Vectors, a Short Message / Tone Only Vector, a Hex / Binary Vector, an Alphanumeric Vector, a Secure Message Vector, and a Short Instruction Vector. Each is described in the following pages. Two of the modes of the Short Instruction Vector is used for assigning temporary addresses that may be associated with a group call. The Numeric, Hex / Binary, Alphanumeric, and Secure Message Vector Packets have associated Message Word Packets in the message field. The host must use the n and b bits of the vector word to calculate what message word locations are associated with the vector. The message word locations and the phase must match. Four of the vectors (Hex / Binary, Alphanumeric, Secure Message, and the temporary address assignment modes of the Short Instruction) enable the FLEX decoder to begin the all frame mode. This mode is required to allow for the decoding of temporary addresses and / or fragmented messages. The host disables the All Frame Mode after the proper time by writing to the decoder via the All Frame Mode Packet. See 12.5.3, Building a Fragmented Message and 12.5.4, Operation of a Temporary Address for more information. For any Address Packet sent to the host (except tone-only addresses), a corresponding Vector Packet will always be sent. If more than two 361 bit errors are detected (via BCH calculations, parity calculations, check character calculations, or value validation) in the vector word the e bit will be set and the message words will not be sent. 1. Numeric Vector Packet Table 12-21 Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 e x n0 Numeric Vector Packet Bit Assignments Bit 6 WN6 p1 x b6 Bit 5 WN5 p0 K3 b5 Bit 4 WN4 x K2 b4 Bit 3 WN3 x K1 b3 Bit 2 WN2 V2 K0 b2 Bit 1 WN1 V1 n2 b1 Bit 0 WN0 V0 n1 b0 V: Vector type identifier. V2 V1 V0 Name 0 1 1 Standard NumericVector Description No special formatting of characters is specified 1 0 0 Special Format Numeric Vector Formatting of the received characters is predetermined by special rules in the host. 1 1 1 Numbered Numeric Vector The received information has been numbered by the service provider to indicate all messages have been properly received WN: Word number of vector (2 - 87 decimal). Describes the location of the vector word in the frame. e: Set if more than 2 bit errors are detected in the word, if the check character calculation fails after error correction has been performed, or if the vector value is determined to be invalid. p: Phase on which the vector was found (0=a, 1=b, 2=c, 3=d) K: Beginning check bits of the message. n: Number of message words in the message including the second vector word for long addresses (000 = 1 word message, 001 = 2 word message, etc.). For long addresses, the first message word is located in the word location that immediately follows the associated vector. b: Word number of message start in the message field (3-87 decimal). For long addresses, the word number indicates the location of the second message word. x: Unused bits. The value of these bits is not guaranteed. 362 2. Short Message / Tone Only Vector Table 12-22 Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 e x d5 Short Message / Tone Only Vector Packet Bit Assignments Bit 6 WN 6 p1 x d4 Bit 5 WN5 p0 d11 d3 Bit 4 WN4 x d10 d2 Bit 3 WN3 x d9 d1 Bit 2 WN 2 V2 d8 d0 Bit 1 WN1 V1 d7 t1 Bit 0 WN 0 V0 d6 t0 V: 010 for a Short Message / Tone Only Vector WN: Word number of vector (2 - 87 decimal). Describes the location of the vector word in the frame. e: Set if more than 2 bit errors are detected in the word or, if after error correction, the check character calculation fails. p: Phase on which the vector was found (0=a, 1=b, 2=c, 3=d) d: Data bits whose definition depend on the value of t in this packet according to the following table. Note that if this vector is received on a long address and the e bit in this packet is not set, the decoder will send a Message Packet from the word location immediately following the Vector Packet. Except for the short message on a non-network address (t=0), all message bits in the Message Packet are unused and should be ignored. t1 t0 00 00 01 10 d1 1 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Description c3 c2 c 1 c 0 b3 b2 b1 b0 a3 a2 a1 a0 Short Numeric: 3 numeric chars*1 when on a messaging address T3 T2 T1 T0 M2 M1 M0 A4 A3 A2 A1 A0 Part of NID when on a Network Address s8 s1 s7 s0 s 6 s 5 s 4 s 3 s 2 s 1 s 0 S2 S1 S0 Tone Only: 8 sources (S) and 9 unused bits (s) R0 N5 N4 N3 N2 N1 N0 S2 S1 S0 Tone Only: 8 sources (S), message number (N), message retrieval flag (R), and 2 unused bits (s) spare message type 11 Note: For long addresses, an extra 5 characters are sent in the Message Packet immediately following the Vector Packet. t: Message type. These bits define the meaning of the d bits in this packet. x: Unused bits. The value of these bits is not guaranteed. 363 3. HEX / Binary, Alphanumeric, and Secure Message Vector Table 12-23 HEX / Binary, Alphanumeric, and Secure Message Vector Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 e x n0 Bit 6 WN 6 p1 x b6 Bit 5 WN5 p0 n6 b5 Bit 4 WN4 x n5 b4 Bit 3 WN3 x n4 b3 Bit 2 WN 2 V2 n3 b2 Bit 1 WN1 V1 n2 b1 Bit 0 WN 0 V0 n1 b0 V: Vector type identifier. V2 V1 V0 000 101 110 Type Secure Alphanumeric Hex / Binary WN: Word number of vector (2 - 87 decimal). Describes the location of the vector word in the frame. e: Set if more than 2 bit errors are detected in the word, if the check character calculation fails after error correction has been performed, or if the vector value is determined to be invalid. p: Phase on which the vector was found (0=a, 1=b, 2=c, 3=d) n: Number of message words in this frame including the first Message word that immediately follows a long address vector. Valid values are 1 through 85 decimal. b: Word number of message start in the message field. Valid values are 3 through 87 decimal. x: Unused bits. The value of these bits is not guaranteed. Note: For long addresses, the first Message Packet is sent from the word location immediately following the word location of the Vector Packet. The b bits indicate the second message word in the message field if one exists. 364 4. Short Instruction Vector Short Instruction Vector Packet Bit Assignments Bit 6 WN 6 p1 x d3 Bit 5 WN5 p0 d 10 d2 Bit 4 WN4 x d9 d1 Bit 3 WN3 x d8 d0 Bit 2 WN 2 V2 d7 i2 Bit 1 WN1 V1 d6 i1 Bit 0 WN 0 V0 d5 i0 Table 12-24 Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 e x d4 V: 001 for a Short Instruction Vector WN: Word number of vector (2 - 87 decimal). Describes the location of the vector word in the frame. e: Set if more than 2 bit errors are detected in the word or, if after error correction, the check character calculation fails. p: Phase on which the vector was found (0=a, 1=b, 2=c, 3=d) d: Data bits whose definition depend on the i bits in this packet according to the following table. Note that if this vector is received on a long address and the e bit in this packet is not set, the decoder will send a Message Packet immediately following the Vector Packet. All message bits in the message packet are unused and should be ignored for all modes except the Temporary address assignment with MSN (i2 i1 i0 =010). i2 0 0 0 0 1 1 1 1 i1 0 0 1 1 0 0 1 1 I0 0 1 0 1 0 1 0 1 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Description a3 a2 a1 a0 f 6 f5 f4 f3 f2 f1 f0 Temporary address assignment* 1 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 11 Event Flags for System Event a3 a2 a1 a0 f 6 N5 N4 N3 N2 N1 N0 Temporary address assignment with MSN* 2 Reserved Reserved Reserved Reserved Reserved for test Notes: 1. Assigned temporary address (a) and assigned frame (f). See 12.5.4, Operation of a Temporary Address for a description of the use of these fields. 2. Assigned temporary address (a), MSb of assigned frame (f 6 ), and message sequence number (N). The message packet sent with this instruction on long addresses contains extra frame information, see 12.5.4, Operation of a Temporary Address for a description and for details on the use of the other fields. 365 i: Instruction type. These bits define the meaning of the d bits in this packet. x: Unused bits. The value of these bits is not guaranteed. 12.4.4 Message Packet The Message Field follows the Vector Field in the FLEX protocol. It contains the message data, checksum information, and may contain fragment numbers and message numbers. If the error bit of a vector word is not set and the vector word indicates that there are message words associated with the page, the message words are sent in Message Packets. The ID of the Message Packet is the word number where the message word was received in the frame. Table 12-25 Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 e i 15 i7 Message Packet Bit Assignments Bit 6 WN 6 p1 i 14 i6 Bit 5 WN5 p0 i 13 i5 Bit 4 WN4 i 20 i 12 i4 Bit 3 WN3 i 19 i 11 i3 Bit 2 WN 2 i 18 i 10 i2 Bit 1 WN1 i 17 i9 i1 Bit 0 WN 0 i 16 i8 i0 WN: Word number of message word (3 - 87 decimal). Describes the location of the message word in the frame. e: Set if more than 2 bit errors are detected in the word. p: Phase on which the message word was found (0=a, 1=b, 2=c, 3=d) i: These are the information bits of the message word. The definitions of these bits depend on the vector type and which word of the message is being received. 12.4.5 Roaming Status Packet The contents of this section apply to the FLEXTM Roaming Decoder. They are not applicable to the FLEXTM Non-Roaming Decoder. The FLEX decoder will automatically prompt the host to read a Roaming Status Packet if RSR, MS1, MFI, MS2, MBI, MAW, NBU, NDR1 , NDR0 , or SCU is set. 366 Table 12-26 Roaming Status Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 RSR x x Bit 6 1 MS1 x x Bit 5 1 MFI x x Bit 4 0 MS2 x x Bit 3 0 MBI x SCU Bit 2 0 MAW x RSC2 Bit 1 0 NBU NDR1 RSC1 Bit 0 0 n NDR0 RSC0 RSR: Re-synchronization Signal Received. Set when the FLEX decoder detected a resynchronization signal and the host configured the FLEX decoder to ignore it via the IRS bit in the roaming control packet. This bit is cleared when read. MS1: Missed Synchronization 1. Set when the FLEX decoder failed to detect the first synchronization pattern (A / A) of a FLEX frame and the FLEX decoder was configured to report missed frame information via the MFC bit in the roaming control packet. This bit is cleared when read. MFI: Missed Frame Information word. Set when the frame information word is received with an uncorrectable number of errors and the FLEX decoder was configured to report missed frame information via the MFC bit in the roaming control packet. This bit is cleared when read. MS2: Missed Synchronization 2. Set when the FLEX decoder failed to detect the second synchronization pattern (C / C) of a frame and FLEX decoder was configured to report missed frame information via the MFC bit in the roaming control packet. This bit is cleared when read. MBI: Missed Block Information word 1. Set when at least one of the block information word ones is received with an uncorrectable number of errors and FLEX decoder was configured to report missed frame information via the MFC bit in the roaming control packet. This bit is set no more than once per frame regardless of the number of missed block information word 1's in the frame. This bit is cleared when read. MAW: Missed Address Word. Set when any address words in the address field is received with an uncorrectable number of errors and FLEX decoder was configured to report missed frame information via the MFC bit in the roaming control packet. This bit is set no more than once per frame regardless of the number of missed address words in the frame. This bit is cleared when read. NBU: Network Bit Update. Set when the NBC bit in the roaming control packet is set and a frame information word is received with a correctable number of errors. This bit will not be set when the frame information word is not received due to missing the first synchronization pattern (A / A). This bit is cleared when read. 367 n: Network bit value. When NBU is set, this is the value of the n bit in the last received frame information word. NDR: Noise Detect Result. These bits indicate the result of a noise detect. The results of noise detects initiated by setting the SND bit in the roaming control packet will always be reported. The results of the automatic noise detects performed in asynchronous mode will only be reported if the RND bit is set in the roaming control packet. When continuous noise detects during block data are enabled by setting the CND bit in the roaming control packet, only the "No FLEX signal detected" result will be reported. These bits are cleared when read. NDR 00 01 10 11 Noise Detect Result No Information Noise Detect was abandoned FLEX signal detected FLEX signal not detected SCU: System Collapse Update. Set when the FLEX decoder is configured for manual collapse mode by setting the MCM bit in the roaming control packet and the system collapse of a frame is received. This bit is set no more than once per frame regardless of the number of phases in the frame. This bit will not be set in frames in which no block information word ones is received properly. This bit is cleared when read. RSC: Received System Collapse. When SCU is set, this value represents the system collapse value that was received in the frame. 368 12.4.6 Receiver Shutdown Packet The contents of this section apply to the FLEXTM Roaming Decoder. They are not applicable to the FLEXTM Non-Roaming Decoder. The Shutdown Packet is sent in both synchronous and asynchronous mode. It is designed to indicate to the host that the receiver is turned off and how much time there is until the FLEX decoder will automatically turn it back on. Table 12-27 Receiver Shut Down Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 FNV TNF 7 FCO Bit 6 1 CF 6 TNF 6 NAF 6 Bit 5 1 CF 5 TNF 5 NAF 5 Bit 4 1 CF 4 TNF 4 NAF 4 Bit 3 1 CF 3 TNF 3 NAF 3 Bit 2 1 CF 2 TNF 2 NAF 2 Bit 1 1 CF 1 TNF 1 NAF 1 Bit 0 1 CF0 TNF 0 NAF 0 FNV: Frame Number Valid. This bit is set if the last decoded frame info word was correctable and the frame number was the expected value. When in asynchronous mode, this value will be 0. CF: Current Frame. When in synchronous mode, this is the current frame number. This value is latched on the negative edge of the READY line when this packet is sent to the host. The value of this field is valid only if the FLEX decoder is in synchronous mode and the FIV bit in the status packet is set. When in asynchronous mode, this value will be 0. TNF: Time to Next Frame. When in synchronous mode TNF indicates the time to the start of the A-word check if the FLEX decoder were to warm up for the next frame. When in asynchronous mode TNF indicates the time to the start of the next automatic noise detect. See "Using the Receiver Shutdown Packet" on page 66 for an explanation on how to use this value. This value is latched on the negative edge of the READY line when this packet is sent to the host. FCO: Frame Carried On. Set if the FLEX decoder is decoding the next frame due to the reception of a non-zero carry-on value in the current or a previous frame. When in asynchronous mode, this value will be 0. NAF: Next Assigned Frame. This is the frame number of the next frame the FLEX decoder was scheduled to decode when the receiver shut down. The value of this field is valid only if the FLEX decoder is in synchronous mode and the FIV bit in the status packet is set. When in asynchronous mode this value will be 0. 369 12.4.7 Status Packet The Status Packet contains various types of information that the host may require. The Status Packet will be sent to the host whenever the FLEX decoder is polled and has no other data to send. The FLEX decoder can also prompt the host to read the Status Packet due to events for which the FLEX decoder was configured to send it (see 12.3.2, Configuration Packet and 12.3.3, Control Packet for a detailed description of the bits). The FLEX decoder will prompt the host to read a Status Packet if the... 1. 2. 3. 4. 5. 6. ... SMU bit in the Status Packet and the SME bit in the Configuration Packet are set. ... MT bit in the Status Packet and the MTE bit in the Configuration Packet are set. ... EOF bit in the Status Packet is set. ... LBU bit in the Status Packet is set. ... EA bit in the Status Packet is set. ... BOE bit in the Status Packet is set. The ID of the Status Packet is 127 (decimal). Table 12-28 Status Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 FIV SM SMU Bit 6 1 f6 LB LBU Bit 5 1 f5 x x Bit 4 1 f4 x MT Bit 3 1 f3 c3 x Bit 2 1 f2 c2 EOF Bit 1 1 f1 c1 EA Bit 0 1 f0 c0 BOE FIV: Frame Info Valid. Set when a valid frame info word has been received since becoming synchronous to the system and the f and c fields contain valid values. If this bit is clear, no valid frame info words have been received since the FLEX decoder became synchronous to the system. This value will change from 0 to 1 at the end of block 0 of the frame in which the 1st frame info word was properly received. It will be cleared when the FLEX decoder goes into asynchronous mode. This bit is initialized to 0 when the FLEX decoder is reset and when the FLEX decoder is turned off by clearing the ON bit in the Control Packet. f: Current frame number. This value is updated every frame regardless of whether the FLEX decoder needs to decode the frame. This value will change to its proper value for a frame at the end of block 0 of the frame. The value of these bits is not guaranteed when FIV is 0. SM: Synchronous Mode. This bit is set when the FLEX decoder is synchronous to the system. The FLEX decoder will set this bit when the first synchronization words are received. It will clear this bit when the FLEX decoder has not properly received both synchronization words in any frame for 8, 16, or 32 minutes (depending on the number of assigned frames and the system 370 collapse). This bit is initialized to 0 when the FLEX decoder is reset and when it is turned off by clearing the ON bit in the Control Packet. LB: Low Battery. Set to the value last read from the LOBAT pin. The host controls when the LOBAT pin is read via the Receiver Control Packets. This bit is initialized to 0 at reset. It is also initialized to the inverse of the LBP bit in the Configuration Packet when the FLEX decoder is turned on by setting the ON bit in the Control Packet. c: Current system cycle number. This value is updated every frame regardless of whether the FLEX decoder needs to decode the frame.This value will change to its proper value for a frame at the end of block 0 of the frame. The value of these bits is not guaranteed when FIV is 0. SMU: Synchronous Mode Update. Set if the SM bit has been updated in this packet. When the FLEX decoder is turned on, this bit will be set when the first synchronization words are found (SM changes to 1) or when the first synchronization search window after the FLEX decoder is turned on expires (SM stays 0). The latter condition gives the host the option of assuming the paging device is in range when it is turned on, and displaying out-of-range only after the initial A search window expires. After the initial synchronous mode update, the SMU bit will be set whenever the FLEX decoder transitions from/to synchronous mode. Cleared when read. Changes in the SM bit due to turning off the FLEX decoder will not cause the SMU bit to be set. This bit is initialized to 0 when the FLEX decoder is reset. LBU: Low Battery Update. Set if the value on two consecutive reads of the LOBAT pin yielded different results. Cleared when read. The host controls when the LOBAT pin is read via the Receiver Control Packets. Changes in the LB bit due to turning on the FLEX decoder will not cause the LBU bit to be set. This bit is initialized to 0 when the FLEX decoder is reset. MT: Minute Time-out. Set if one minute has elapsed. Cleared when read. This bit is initialized to 0 when the FLEX decoder is reset. EOF: End Of Frame. Set when the FLEX decoder is in all frames mode and the end of frame has been reached. The FLEX decoder is in all frames mode if the all frames mode enable counter is non-zero, if any temporary address enabled counter is non-zero, or if the FAF bit in the All Frame Mode Packet is set. Cleared when read. This bit is initialized to 0 when the FLEX decoder is reset. EA: End of Addresses. If EAE of the control packet is set and an address is detected in a frame, EA will be set after the FLEX decoder processes the last address in the frame. Since data packets take priority over the status packet, the status packet with the EA bit set is guaranteed to come after all address packets for the frame. Cleared when read. This bit is initialized to 0 when the FLEX decoder is reset. BOE: Buffer Overflow Error. Set when information has been lost due to slow host response time. When the data packet FIFO transmit buffer on the FLEX decoder overflows, the FLEX decoder clears the buffer, turns off decoding by clearing the ON bit in the Control Packet, and sets this bit. Cleared when read. This bit is initialized to 0 when the FLEX decoder is reset. 371 x: Unused bits. The value of these bits is not guaranteed. 12.4.8 Part ID Packet The Part ID Packet is sent by the FLEX decoder whenever the FLEX decoder is disabled due to the checksum feature. See 12.3.1, Checksum Packet for a description of the checksum feature. Since the FLEX decoder is disabled after reset, this is the first packet that will be received by the host after reset. The ID of the Part ID Packet is 255 (decimal). Table 12-29 Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 1 MDL 1 CID 7 REV 7 Part ID Packet Bit Assignments Bit 6 1 MDL0 CID 6 REV 6 Bit 5 1 CID 13 CID 5 REV 5 Bit 4 1 CID 12 CID4 REV 4 Bit 3 1 CID 11 CID 3 REV 3 Bit 2 1 CID 10 CID 2 REV 2 Bit 1 1 CID 9 CID 1 REV 1 Bit 0 1 CID 8 CID 0 REV 0 MDL: Model. This identifies the FLEX decoder model. Current value is 0. CID: Compatibility ID. This value describes the FLEX decoders to which this part is backwards compatible. See table below for meaning and current value. Bit CID0 CID1 CID2 Indicates this IC can be used in place of FLEX Alphanumeric Decoder I* 1 FLEX Roaming Decoder I* FLEX Numeric Decoder 2 Value for FLEXTM Roaming Decoder II 1 (TRUE) 1 (TRUE) 0 (FALSE) Notes: 1. Compatibility to FLEX Alphanumeric Decoder II is indicated by MDL set to 0, CID 0 set to 1, and REV greater than or equal to 7. 2. Compatibility to FLEX Roaming Decoder II is indicated by MDL set to 0, CID 1 set to 1, and REV greater than or equal to 8. REV: Revision. This identifies the revision and manufacturer of the FLEX decoder. The following table lists the currently available part ID's of the FLEX decoder family. 372 Part ID Packet (Hex) 00 01 03 00 01 04 00 01 06 00 01 07 00 01 08 00 03 03 00 03 05 00 03 09 00 03 0A 00 04 01 00 01 15 00 03 15 Revision FLEX Alphanumeric Decoder I FLEX Alphanumeric Decoder I FLEX Alphanumeric Decoder I FLEX Alphanumeric Decoder II FLEX Alphanumeric Decoder II FLEX Roaming Decoder I FLEX Roaming Decoder I FLEX Roaming Decoder II FLEX Roaming Decoder II FLEX Numeric Decoder FLEX Alphanumeric Decoder II FLEX Roaming Decoder II Manufacturer Texas Instruments Motorola Semiconductor Products Sector Philips Motorola Semiconductor Products Sector Texas Instruments Motorola Semiconductor Products Sector Texas Instruments Motorola Semiconductor Products Sector Texas Instruments Texas Instruments Hitachi Hitachi 373 12.5 12.5.1 Application Notes Receiver Control Introduction: The FLEX decoder has 8 programmable receiver control lines (S0-S7). The host has control of the receiver warm up and shut down timing as well as all of the various settings on the control lines through configuration registers on the FLEX decoder. The configuration registers for most settings allow the host to configure what setting is applied to the control lines, how long to apply the setting, and if the LOBAT input pin is polled before changing from the setting. With this programmability, the FLEX decoder should be able to interface with many off-the-shelf receiver ICs. When using the internal demodulator (i.e. when the IDE bit of the configuration packet is set), the S0 pin becomes the input for the demodulator and the S0 register setting in the receiver control configuration packets controls the tracking mode of the peak and valley detectors for the internal data slicer. When the S0 bit is set in a receiver setting, the internal data slicer will be in fast track mode. When the S0 bit is cleared in a receiver setting, the internal data slicer will be in slow track mode. For details on the configuration of the receiver control settings, see 12.3.9, Receiver Control Configuration Packets. 1. Receiver Settings at Reset The receiver control ports are three-state outputs which are set to the high-impedance state when the FLEX decoder is reset and until the corresponding FRS bit in the Receiver Line Control Packet is set or until the FLEX decoder is turned on by setting the ON bit in the Control Packet. This allows the designer to force the receiver control lines to the receiver off setting with external pullup or pull-down resistors before the host can configure these settings in the FLEX decoder. When the FLEX decoder is turned on, the receiver control ports are driven to the settings configured by the "12.3.9 Receiver Control Configuration Packets" until the FLEX decoder is reset again. 2. Automatic Receiver Warm Up Sequence The FLEX decoder allows for up to 6 steps associated with warming up the receiver. When the FLEX decoder automatically turns on the receiver, it starts the warm up sequence 160 ms before it requires valid signals at the EXTS0 and EXTS1 input pins (or the equivalent internal signals when using the internal demodulator/data slicer). The first step of the warm up sequence involves leaving the receiver control lines in the "Off" state for the amount of time programmed for "Warm Up Off Time". At the end of the "Warm Up Off Time", the first warm up setting, if enabled, is applied to the receiver control lines for the amount of time programmed for that setting. Each subsequent warm up setting is applied to the receiver control lines for their corresponding time until a disabled warm up setting is found. At the end of the last used warm up setting, the "1600sps Sync Setting" or the "3200sps Sync Setting" is applied to the receiver control lines depending on the current state of the FLEX decoder. The sum total of all of the used warm up times and the "Warm Up Off Time" must not exceed 160ms. If it exceeds 160ms, the FLEX decoder will execute the receiver shut down sequence at the end of the 160ms warm up period. 374 The receiver warm up sequence while decoding when all warm up settings are enabled is shown in figure 12-9. 160 ms Warm Up Off Time RECEIVER CONTROL LINE SETTING Warm Up Time 1 Warm Up Setting 1 Warm Up Time 2 Warm Up Setting 2 Warm Up Time 3 Warm Up Setting 3 Warm Up Time 4 Warm Up Setting 4 Warm Up Time5 Warm Up Setting 5 1600sps or 3200sps Sync Setting Off Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check EXTS1 & EXTS0 signals are expected to be valid here. Figure 12-9 Automatic Receiver Warm Up Sequence 3. Host Initiated Receiver Warm Up Sequence The host can cause the FLEX decoder to warm-up the receiver in three ways: (1) by turning on the FLEX decoder by setting the ON bit in the control packet; (2) by requesting a noise detect by setting the SND bit in the roaming control packet; or (3) by requesting an A-word search by setting the SAS bit in the roaming control packet. When the FLEX decoder warms up the receiver in response to a host request, the first warm up setting, if enabled, is applied to the receiver control lines for the amount of time programmed for that setting. Each subsequent warm up setting is applied to the receiver control lines for their corresponding time until a disabled warm up setting is found. Once a disabled warm up setting is found, the "3200sps Sync Setting" (for ON and SND warm ups) or the "1600sps Sync Setting" (for SAS warm ups) is applied to the receiver control lines and the decoder does not expect valid signal until after the "3200sps Sync Warm Up Time" (for ON, SND, and SAS warm ups) has expired. In figure 12-10 the receiver warm up sequence when the host initiates a warm-up sequence and when all warm up settings are enabled is shown. Warm Up Time Sync 3200sps 3200sps Sync Setting Warm Up Time 1 RECEIVER CONTROL LINE SETTING Warm Up Setting 1 Warm Up Time 2 Warm Up Setting 2 Warm Up Time 3 Warm Up Setting 3 Warm Up Time 4 Warm Up Setting 4 Warm Up Time5 Warm Up Setting 5 Off Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check EXTS1 & EXTS0 signals are expected to be valid here. Figure 12-10 Host Initiated Receiver Warm Up Sequence 375 4. Receiver Shut Down Sequence The FLEX decoder allows for up to 3 steps associated with shutting down the receiver. When the FLEX decoder decides to turn off the receiver, the first shut down setting, if enabled, is applied to the receiver control lines for the corresponding shut down time. At the end of the last used shut down time, the "Off" setting is applied to the receiver control lines. If the first shut down setting is not enabled, the FLEX decoder will transition directly from the current on setting to the "Off" setting. The receiver turn off sequence when all shut down settings are enabled is shown in figure 12-11. If the receiver is on or being warmed up when the decoder is turned off (by clearing the ON bit in the Control Packet), the FLEX decoder will execute the receiver shutdown sequence. If the FLEX decoder is executing the shut down sequence when the FLEX decoder is turned on (by setting the ON bit in the Control Packet), the FLEX decoder will complete the shut down sequence before starting the warm up sequence. Shut Down Time 1 RECEIVER CONTROL LINE SETTING 1600sps or 3200sps Sync or Data Setting Shut Down Setting 1 Shut Down Time 2 Shut Down Setting 2 Off Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Figure 12-11 5. Miscellaneous Receiver States Receiver Shut Down Sequence In addition to the warm up and shut down states, the FLEX decoder has four other receiver states. When these settings are applied to the receiver control lines, the FLEX decoder will be decoding the EXTS1 and EXTS0 input signals (or the equivalent internal signals when using the internal demodulator/data slicer). The timing of these signals and their duration depends on the data the FLEX decoder decodes. The four settings are as follows: * 1600sps Sync Setting:This setting is applied when the FLEX decoder is searching for a 1600 symbols per second signal. * 3200sps Sync Setting:This setting is applied when the FLEX decoder is searching for a 3200 symbols per second signal. * 1600sps Data Setting:This setting is applied after the FLEX decoder has found the C or C sync word in a 1600 symbols per second frame. 376 * 3200sps Data Setting:This setting is applied after the FLEX decoder has found the C or C sync word in a 3200 symbols per second frame. Some examples of how these settings will be used in the FLEX decoder are shown in figure 12-12. Frame Info FLEX SIGNAL Block 10 Sync 1 Sync 2 Block 0 RECEIVER CONTROL LINE SETTING EXAMPLE #1 1600 sps Data or 3200 sps Data or Last Used Warm Up Setting 1600 sps Sync Setting 3200sps Sync Setting 3200sps Data Setting Possible LOBAT Check RECEIVER CONTROL LINE SETTING EXAMPLE #2 1600 sps Data or 3200 sps Data or Last Used Warm Up Setting Possible LOBAT Check 1600sps Sync Setting Possible LOBAT Check 1600 sps Data Setting Possible LOBAT Check Possible LOBAT Check Figure 12-12 6. Low Battery Detection Examples of Receiver Control Transitions The FLEX decoder can be configured to poll the LOBAT input pin at the end of every receiver control setting. This check can be enabled or disabled for each receiver control setting. If the poll is enabled for a setting, the pin will be read just before the FLEX decoder changes the receiver control lines from that setting to another setting. The FLEX decoder will send a Status Packet whenever the value on two consecutive reads of the LOBAT pin yields different results. 12.5.2 Message Building A simple message consists of an Address Packet followed by a Vector Packet indicating the word numbers of associated Message Packets.The tables below show a more complex example of receiving three Messages and two Block Information Word Packets in the first two blocks of a 2 phase 3200 bps, FLEX frame. Note that the messages shown may be portions of fragmented or group messages. Note further that in the case of a 6400 bps FLEX signal, there would be four phases: A, B, C and D, and in the case of a 1600 bps signal there would be only a single phase A. Table 12-30 shows the block number, word number (WN) and word content of both phases A and C. Note contents of words not meant to be received by the host are left blank. Each phase begins with a block information word (WN 0), this is not sent to the host. The first message is in phase A and has an address (WN 3), vector (WN 7) and three message words (WN9 - 11). The second message is also in phase A and has an address (WN 4), a vector (WN 8) and four message words 377 (WN 12 - 15). The third message is in phase C and has a 2 word long address (WN 5 - 6) followed by a vector (WN 10) and three message words. Since the third message is sent on a long address, the first message word (WN 11) begins immediately after the vector. The vector indicates the location of the second and third message words (WN 14 - 15). Table 12-30 FLEX SIGNAL BLOCK 0 Word Number 0 1 3 4 5 6 7 1 8 9 10 11 12 13 14 15 VECTOR 1 VECTOR 2 MESSAGE 1,1 MESSAGE 1,2 MESSAGE 1,3 MESSAGE 2,1 MESSAGE 2,2 MESSAGE 2,3 MESSAGE 2,4 MESSAGE 3,2 MESSAGE 3,3 VECTOR 3 MESSAGE 3,1 ADDRESS 1 ADDRESS 2 LONG ADDRESS 3 WORD 1 LONG ADDRESS 3 WORD 2 PHASE A BIW1 PHASE C BIW1 BIW BIW Table 12-31 shows the sequence of packets received by the host. The FLEX decoder processes the FLEX signal one block at a time, and one phase at a time. Thus, the address and vector information in block 0 phase A is sent to the host in packets 1-3. Then information in block 0 phase C, two block information words and one long address, is sent to the host in packets 4-6. Packets 7 - 18 correspond to information in block 1, processed in phase A first and phase C second. 378 Table 12-31 FLEX DECODER PACKET SEQUENCE WORD NUMBER N.A. (7) N.A. (8) 7 N.A. N.A. N.A. (10) 8 9 10 11 12 13 14 15 10 11 14 15 PACKET PACKET TYPE 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th 15th 16th 17th 18th ADDRESS ADDRESS VECTOR BIW BIW LONG ADDRESS VECTOR MESSAGE MESSAGE MESSAGE MESSAGE MESSAGE MESSAGE MESSAGE VECTOR MESSAGE MESSAGE MESSAGE PHASE A A A C C C A A A A A A A A C C C C COMMENT Address 1 has a vector located at WN 7 Address 2 has a vector located at WN 8 Vector for Address 1: Message Words located at WN = 9 to 11, phase A If BIWs enabled, then BIW packet sent If BIWs enabled, then BIW packet sent Long Address 3 has a vector beginning in word 10 of phase C Vector for Address 2: Message Words located at WN = 12 to 15, phase A Message information for Address 1 Message information for Address 1 Message information for Address 1 Message information for Address 2 Message information for Address 2 Message information for Address 2 Message information for Address 2 Vector for Long Address 3: Message Words located at WN = 14 - 15, phase C Second word of Long Vector is first message information word of Address 3 Message information for Address 3 Message information for Address 3 The first message is built by relating packets 1, 3, and 8-10. The second message is built by relating packets 2, 7 and 11 - 14. The third message is built by relating packets 6 and 15 - 18. Additionally, the host may process block information in packets 4 and 5 for time setting information. 12.5.3 Building a Fragmented Message The longest message which will fit into a frame is 84 code words total of message data. Three alpha characters per word yields a maximum message of 252 characters in a frame assuming no other traffic. Messages longer than this value must be sent as several fragments. 379 Additional fragments can be expected when the "continue bit" in the 1st Message Word is set. This causes the pager to examine every following frame for an additional fragment until the last fragment with the continue bit reset is found. The only requirement relating to the placement in time of the remaining fragments is that no more than 32 frames (1 minute) or 128 frames (4 minutes) as indicated by the service provider may pass between fragment receptions. Each fragment contains a check sum character to detect errors in the fragment, a fragment number 0, 1, or 2 to detect missing fragments, a message number to identify which message the fragment is a part, and the continue bit which either indicates that more fragments are in queue or that the last fragment has been received. The following describes the sequence of events between the Host and the FLEX decoder required to handle a fragmented message: * The host will receive a vector indicating one of the following types: V2 V1 V0 000 101 110 Type Secure Alphanumeric Hex / Binary * The FLEX decoder will increment the all frame mode counter inside the FLEX decoder and begin to decode all of the following frames. * The host will receive the Message Packet(s) contained within that frame followed by a Status Packet. The host must decide based on the Message Packet to return to normal decoding operation. If the message is indicated as fragmented by the Message Continued Flag "C" being set in the Message Packet then the host does not decrement the all frame mode counter at this time. The host decrements the counter if the Message Continued Flag "C" is clear by writing the All Frame Mode Packet to the FLEX decoder with the "DAF" bit = 1. If no other fragments, temporary addresses are pending and the FAF bit is clear in the All Frame Mode Register, then the FLEX decoder returns to normal operation. * The FLEX decoder continues to decode all of the frames and passes any address infor-mation, vector information and message information to the host followed by a status packet indicating the end of the frame. If the message is indicated as fragmented by the Message Continued Flag "C" in the Message Packet then the host remains in the receive mode expecting more information from the FLEX decoder. * After the host receives the second and subsequent fragment with the Message Continued Flag "C" = 1, it should decrement the all frame mode counter by sending an All Frame Mode Packet to the FLEX decoder with the "DAF" bit = 1. Alternatively, the host may choose to decrement the counter at the end of the entire message by decrementing the counter once for each fragment received. * When the host receives a Message Packet with the Message Continued Flag "C" = 0, it will send two All Frame Mode Packets to the FLEX decoder with the "DAF" bit = 1. The two 380 packets decrement the count for the first fragment and the last fragment. This dec-rements the all frame counter to zero, if no other fragmented messages, temporary addresses are pending and the FAF bit is clear in the All Frame Mode Register, the FLEX decoder returns to normal operation. * The above process must be repeated for each occurrence of a fragmented message. The host must keep track of the number of fragmented messages being decoded and insure the all frame mode counter decrements after each fragment or after each fragmented message. Table 12-32 Alphanumeric Message without fragmentation PACKET 1st 2nd 3rd 4th Note: * PACKET TYPE ADDRESS 1 VECTOR 1 MESSAGE Variable* PHASE A A A All Frame Counter COMMENT 0 1 1 0 Address 1 is received Vector = Alphanumeric Type Message Word received "C" bit = 0, No more fragments are expected. Host writes All Frame Mode Packet to the FLEX decoder with the "DAF" bit = 1 Host Initiated Packet. The FLEX decoder returns a packet according to 12.4, Decoderto-Host Packet Descriptions. 381 Table 12-33 Alphanumeric Message with fragmentation PACKET 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th Note: * PACKET TYPE ADDRESS 1 VECTOR 1 MESSAGE STATUS ADDRESS 1 VECTOR 1 MESSAGE Variable* STATUS ADDRESS 1 VECTOR 1 MESSAGE Variable* Variable* A A A B B B PHASE A A A All Frame Counter COMMENT 0 1 1 1 1 2 2 1 1 1 2 2 1 0 Address 1 is received Vector = Alphanumeric Type Message Word received "C" bit = 1, Message is fragmented, more expected End of Frame Indication (EOF = 1) Address 1 is received Vector = Alphanumeric Type Message Word received "C" bit = 1, Message is fragmented, more expected. Host writes All Frame Mode Packet to the FLEX decoder with the "DAF" bit = 1 End of Frame Indication (EOF = 1) Address 1 is received Vector = Alphanumeric type Message Word received "C" bit = 0, No more fragments are expected. Host writes All Frame Mode Packet to the FLEX decoder with the "DAF" bit = 1 Host writes All Frame Mode Packet to the FLEX decoder with the "DAF" bit = 1 Host Initiated Packet. The FLEX decoder returns a packet according to 12.4, Decoderto-Host Packet Descriptions. 12.5.4 Operation of a Temporary Address 1. Group Messaging The FLEX protocol allows for a dynamic group call for the purpose of sending a common message to a group of paging devices. The dynamic group call approach assigns a "Temporary Address" using the personal address and the short instruction vector. The FLEX protocol specifies sixteen addresses for the dynamic group call which may be temporarily activated in a future frame (If the frame or one of the frames designated is equal to the present frame the host is to interpret this as the next occurrence of this frame 4 minutes in the future.) The temporary address is valid for one message starting in the specified frame(s) and remaining valid throughout the following frames to the completion of the message. If the message is not found in the specified frame(s) the host must disable the assigned temporary address. 382 The following describes the sequence of events between the Host and the FLEX decoder required to handle a temporary address: * Following an Address Packet, the host will receive a Vector Packet with V2 V1 V0 = 001 and i2 i1 i0 = 000 or 010 (a Short Instruction Vector indicating a temporary address has been assigned to this pager). The system may send either and i 2 i1 i0 = 000 or and i2 i1 i0 = 010 or both when assigning a temporary address. The vector packet with and i2 i1 i0 = 000 will indicate which temporary address is assigned and the frame in which the temporary address is expected. The vector packet with and i2 i1 i0 = 010 will indicate which temporary address is assigned, the MSb of the expected frame (essentially indicating 64 frames in which to look for the temporary address), and a message sequence number. When the vector packet with and i2 i1 i0 = 010 is received on a long address, the specific assign frame is included in the mes-sage word sent after the vector. * The FLEX decoder will increment the corresponding temporary address counter for each temporary address assignment vector received and begin to decode all of the follow-ing frames. Note that this implies a single dynamic group assignment that is implemented by sending two short instructions (one for each temporary address assignment mode of the short instruction vector) will cause the corresponding temporary address counter to incre-ment twice. * The FLEX decoder continues to decode all of the frames and passes any address infor-mation, vector information and message information to the host followed by a status packet indicating the end of each frame and the current frame number. There are several scenarios which may occur with temporary addresses. 1. The temporary address is not found in the any of the assigned frames and therefore the host must terminate the temporary address mode by sending an All Frame Mode Packet to the FLEX decoder with the "DTA" bit of the particular temporary address set (if both temporary address assignment packets were used to assign the temporary address, the "DTA" bit must be set twice to disable the temporary address). 2. The temporary address is found in the frame it was assigned and was not a fragmented message. Again, the host must terminate the temporary address mode by sending an All Frame Mode Packet to the FLEX decoder with the "DTA" bit of the particular temporary address set (if both temporary address assignment packets were used to assign the temporary address, the "DTA" bit must be set twice to disable the temporary address). 3. The temporary address is found in the assigned frame and it is a fragmented message. In this case, the host must follow the rules for Operation of a Fragmented Message and determine the proper time to stop the all frame mode operation. In this case, the host must write to the "DAF" bit with a "1" and the appropriate "DTA" bit with a "1" in the All Frame Mode Register in order to terminate both the fragmented message and the temporary address (if both temporary address assignment packets were used to assign the temporary address, the "DTA" bit must be set twice to disable the temporary address). 383 * The above operation is repeated for every temporary address. 12.5.5 Using the Receiver Shutdown Packet The contents of this section apply to the FLEXTM Roaming Decoder. They are not applicable to the FLEXTM Non-Roaming Decoder. 1. Calculating Time Left The receiver shutdown packet gives timing information to the host. Two times are of particular interest when implementing a roaming algorithm. * TimeToWarmUpStart. Defined as the amount of time there is before the receiver will start to warm up (i.e. transition from the off state to the first warm up state). * TimeToTasksDisabled. Defined as the amount of time the host has to complete any host initiated tasks (e.g. by setting SND or SAS in the roaming control packet). The formula's for calculating these times depend on whether the FLEX decoder is in synchronous mode or asynchronous mode. SYNCHRONOUS MODE: TimeToWarmUpStart (TNF * 80ms) + (SkippedFrames * 1874.375ms) + ReceiverOffTime -167.5ms TimeToTasksDisabled (TNF * 80ms) + (SkippedFrames * 1874.375ms) - 247.5ms ASYNCHRONOUS MODE: TimeToWarmUpStart ((TNF -2) * 80ms) + ReceiverOffTime TimeToTasksDisabled ((TNF -3) * 80 ms) Where, TNF: SkippedFrames: Time to Next Frame. Value from the receiver shutdown packet. The number of frames that won't be decoded. This can be calculated from the Current Frame (CF) and Next Needed Frame (NAF) fields in the receiver shutdown packet (e.g. If CF is 10 and NAF is 12, then SkippedFrames is 1) The time programmed in the receiver off setting packet. ReceiverOffTime: 384 2. Calculating How Long Tasks Take Since the TimeToTaskDisabled discussed in the previous section limits how much the host can do while the FLEX decoder is battery saving, it is necessary for the host to know how long it can take the FLEX decoder to perform a task. The formulas below calculate how long the two types of host initiated tasks take to complete as measured from the last SPI clock of the packet that initiates the task to the time the receiver shutdown sequence starts. Note that the receiver shutdown sequence must start before tasks are disabled. The following formula calculates how long it will take to complete a Noise Detect started by setting the SND bit in the roaming control packet. This formula assumes that (1) the noise detect was performed while in synchronous mode or (2) the noise detect was performed in asynchronous mode and did not find FLEX signal or (3) the noise detect found FLEX signal but the DAS bit of the roaming control packet was set. TimeToPerformNoiseDetect TotalWarmUpTime + 82ms Where, TotalWarmUpTime: The sum of the times programmed for the used warm up steps plus the time programmed for the 3200sps Sync Setting in the receiver control configuration packets. The following formula calculates how long it will take to complete an A-word search initiated by setting the SAS bit in the roaming control packet. This formula assumes that the A-word search failed to find roaming FLEX channel. TimeToPerformAwordSearch TotalWarmUpTime + AST + 47ms Where, TotalWarmUpTime: The sum of the times programmed for the used warm up steps plus the time programmed for the 3200sps Sync Setting in the receiver control configuration packets. AST: The value configured using the timing control packet. The following formula calculates how long it will take to complete a Noise Detect/A-word search combination. This can occur when the noise detect is performed while in asynchronous mode, the noise detect finds FLEX signal, and the DAS bit of the roaming control packet is not set. TimeToPerformBoth TotalWarmUpTime + AST +127ms Where, 385 TotalWarmUpTime: The sum of the times programmed for the used warm up steps plus the time programmed for the 3200sps Sync Setting in the receiver control configuration packets. AST: The value configured using the timing control packet. 386 12.6 Timing Diagrams (Reference Data) The following diagrams show the timing in a standalone FLEXTM Decoder IC. They do not apply to this LSI, and should be used only for reference. 12.6.1 SPI Timing The following diagram and table describe the timing specifications of the SPI interface. SS READY tSSH tRDY tLEAD2 tLEAD1 SCK tCYC tR tF tLAG2 tLAG1 tRH tRS tSCKL MISO Hi-Z tSCKH D31 D0 Hi-Z tAC MOSI D31 tHI tSU tV tHO D0 tDIS Figure 12-13 SPI Timing 387 Table 12-34 SPI Timing (VDD = 1.8 V to 3.6 V, TA = -20C to 75C) Characteristic Operating Frequency Cycle Time Select Lead Time De-select Lag Time Select-to-Ready Time Select-to-Ready Time Re-select Time Ready High Time Ready Lead Time Not Ready Lag Time MOSI Data Setup Time MOSI Data Hold Time MISO Access Time MISO Disable Time MISO Data Valid Time MISO Data Hold Time SS High Time SCK High Time SCK Low Time SCK Rise Time SCK Fall Time 20% to 70% VDD 20% to 70% VDD CL =50pf CL =50pf CL =50pf previous packet did not program an address word* 2 CL =50pf Conditions Symbol f OP tCYC t LEAD1 t LAG1 t RDY Min*1 Max* 1 Unit dc 1000 200 200 80 420 30 50 200 200 200 200 0 200 300 200 0 200 300 300 1 1 1 MHz ns ns ns s s s s ns ns ns ns ns ns ns ns ns ns ns s s previous packet programmed an address t RDY word*2 CL =50pf previous packet was a checksum/special t RS packet* 3 CL =50pf t RH t LEAD2 t LAG2 t SU t HI t AC t DIS tV t HO t SSH t SCKH t SCKL tR tF Notes: 1. The specifications given in this data sheet indicate the minimum performance level of all FLEX decoders regardless of manufacturer. Individual manufacturers may have better performance than indicated. 2. When the host re-programs an address word with a Host-to-Decoder packet ID > 127 (decimal), there may be an added delay before the FLEX decoder is ready for another packet. 3. When the host sends a checksum packet (ID is 00) or a special packet (ID is 1C through 1F hex) the t RS specification applies, otherwise the timing specifications for t LAG1 and tSSH govern the re-select timing. 388 12.6.2 Start-up Timing The following diagram and table describe the timing specifications of the FLEX decoder when power is applied. VDD tSTART Oscillator RESET tRESET READY tRHRL Figure 12-14 Start-up Timing Table 12-35 Start-up Timing (V DD = 1.8 V to 3.6 V, TA = -20C to 75C) Characteristic Oscillator Start-up Time RESET Hold Time RESET High to READY Low Conditions Symbol t START t RESET t RHRL 200 76,800 76,800 Min*1 Max * 1 5 Unit sec ns T*2 Notes: 1. The specifications given in this data sheet indicate the minimum performance level of all manufacturers of the FLEX decoder. Individual manufacturers may have better performance than indicated. 2. T is one period of the o DEC clock source. Note that from power-up, the oscillator start-up time can impact the availability and period of clock strobes. This can affect the actual RESET high to READY low timing. 389 12.6.3 Reset Timing The following diagram and table describe the timing specifications of the FLEX decoder when it is reset. RESET tRL READY tRLRH tRHRL Figure 12-15 Reset Timing Table 12-36 Reset Timing (VDD = 1.8 V to 3.6 V, TA = -20C to 75C) Characteristic RESET Pulse Width RESET Low to READY High RESET High to READY Low Conditions Symbol t RL t RLRH t RHRL Min*1 200 - 76,800 Max * 1 - 200 76,800 Unit ns ns T*2 Notes: 1. The specifications given in this data sheet indicate the minimum performance level of all manufacturers of the FLEX decoder. Individual manufacturers may have better performance than indicated. 2. T is one period of the o DEC clock source. 390 Section 13 Electrical Characteristics 13.1 Absolute Maximum Ratings Table 13-1 lists the absolute maximum ratings. Table 13-1 Absolute Maximum Ratings Item Power supply voltage Analog power supply voltage Programming voltage Input voltage Ports other than Port B Port B Operating temperature Storage temperature Symbol VCC AVCC VPP Vin AVin Topr Tstg Value -0.3 to +7.0 -0.3 to +7.0 -0.3 to +13.0 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -20 to +75 -55 to +125 Unit V V V V V C C Note: Permanent damage may occur to the chip if maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. 391 13.2 13.2.1 Electrical Characteristics Power Supply Voltage and Operating Range The power supply voltage and operating range of the H8/3937 Series and H8/3937R Series are indicated by the shaded region in the figures. 1. Power supply voltage and oscillator frequency range fosc (MHz) fW (kHz) 3.6 VCC (V) * Active (high-speed) mode * Sleep (high-speed) mode Note: fosc is the frequency when an oscillator element or external clock is used. 10.0 4.0 2.0 1.8 2.7 1.8 3.6 VCC (V) * All operating modes 160 76.8 392 2. Power supply voltage and operating frequency range 5.0 o (MHz) 40 19.2 oSUB (kHz) 1.8 2.7 3.6 VCC (V) * Active (high-speed) mode * Sleep (high-speed) mode (except CPU) 625 o (kHz) 10 4.8 1.8 3.6 2.0 1.0 20 9.6 250 VCC (V) * Subactive mode * Subsleep mode (except CPU) * Watch mode (except CPU) 15.625 1.8 2.7 3.6 VCC (V) * Active (medium-speed) mode (except A/D converter) * Sleep (medium-speed) mode (except A/D converter) 3. Analog power supply voltage and A/D converter operating range 625 o (MHz) 5.0 o (kHz) 3.6 AVCC (V) * Active (high-speed) mode * Sleep (high-speed) mode 500 1.0 1.8 2.7 1.8 2.7 3.6 AVCC (V) * Active (medium-speed) mode * Sleep (medium-speed) mode 393 13.2.2 DC Characteristics Table 13-2 lists the DC characteristics of the H8/3937 Series and H8/3937R Series. Table 13-2 DC Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C (including subactive mode) unless otherwise indicated. Values Item Symbol Applicable Pins RES, WKP0 to WKP 7, IRQ1 to IRQ4, TMIC, TMIF, TMIG, SCK31 , SCK32, ADTRG RXD31 , RXD32, UD OSC1 DX1 P10 to P17, P30 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P93, PA 0 to PA3 PB 0 to PB7 IFIN Min 0.9 V CC Typ -- Max VCC + 0.3 Unit Test Condition V Notes Input VIH high voltage 0.8 V CC 0.9 V CC 0.9 V CC 0.8 V CC -- -- -- -- VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 V V V V 0.8 V CC 0.9 V CC -- -- -- -- AV CC + 0.3 V VCC + 0.3 VCC + 0.3 0.1 V CC V V V EXTS0, EXTS1, LOBAT 0.8 V CC Input VIL low voltage RES, WKP0 to WKP 7, IRQ1 to IRQ4, TMIC, TMIF, TMIG, SCK31 , SCK32, ADTRG RXD31 , RXD32, UD OSC1 DX1 P10 to P17, P30 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P93, PA 0 to PA3 PB 0 to PB7 IFIN -0.3 -0.3 -0.3 -0.3 -0.3 -- -- -- -- 0.2 V CC 0.1 V CC 0.1 V CC 0.2 V CC V V V V -0.3 -0.3 -- -- -- 0.2 V CC 0.1 V CC 0.2 V CC V V V EXTS0, EXTS1, LOBAT -0.3 Note: Connect the TEST and TESTD pins to VSS. 394 Values Item Symbol Applicable Pins Min Typ -- Max -- Unit Test Condition V -I OH = 0.1 mA Notes Output VOH high voltage P10 to P17, P30 to P37, VCC - 0.3 P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P93, PA 0 to PA3 CLKOUT VCC - 0.5 VCC - 0.5 SYMLCK, S0 to S7 VCC - 0.5 VCC - 0.3 -- -- -- -- -- -- -- -- -- 0.5 V V V V V VCC = 2.5 V to 3.6 V -I OH = 1.5 mA -I OH = 1.0 mA VCC = 2.5 V to 3.6 V -I OH = 0.4 mA -I OH = 0.1 mA IOL = 0.4 mA Output VOL low voltage P10 to P17, P30 to P37, -- P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P93, PA 0 to PA3 CLKOUT -- -- SYMCLK, S0 to S7 -- -- -- -- -- -- -- -- -- 0.5 0.5 0.5 0.3 20.0 1.0 1.0 V V V V A VCC = 2.5 V to 3.6 V IOL = 1.5 mA IOL = 1.0 mA VCC = 2.5 V to 3.6 V IOL = 0.4 mA IOL = 0.1 mA VIN = 0.5 V to VCC - 0.5 V *2 *1 Input/ | I IL | output leakage current RES -- -- OSC1, DX 1, P10 to -- P17, P30 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P93, PA0 to PA 3 PB 0 to PB7 EXTS1, EXTS0, LOBAT, IFIN -- -- A VIN = 0.5 V to VCC - 0.5 V -- -- -- 1.0 1.0 120 A VIN = 0.5 V to AV CC - 0.5 V VIN = 0.5 V to VCC - 0.5 V VCC = 3 V, VIN = 0 V Pull-up -Ip MOS current Input CIN capacitance P10 to P17, P30 to P37, 10 P50 to P57, P60 to P67 All input pins except power supply, RES, PB 0 to PB7 RES -- -- 15.0 pF f = 1 MHz, VIN =0 V, Ta = 25C *2 *1 -- -- -- -- -- 80.0 15.0 15.0 PB 0 to PB7 -- 395 Values Item Symbol Applicable Pins VCC Min -- Typ 0.8 Max -- Unit Test Condition mA Active (high- speed) mode VCC = 3 V, fOSC = 2 MHz Active (mediumspeed) mode VCC = 3 V, fOSC = 2 MHz, oOSC/128 VCC = 3 V, fOSC = 2 MHz Notes *3 *4 Reference value *3 *4 Reference value *3 *4 Reference value *3 *4 Reference value *3 *4 Reference value *3 *4 Reference value *3 *4 Active IOPE1 mode current dissipation IOPE2 VCC -- 0.25 -- mA Sleep ISLEEP mode current dissipation SubISUB active mode current dissipation SubISUBSP sleep mode current dissipation Watch IWATCH mode current dissipation RAM VRAM data retaining voltage VCC -- 0.45 -- mA VCC -- 56 -- A VCC = 2.7 V, 160-kHz crystal oscillator (o SUB=oW /2) VCC -- 30 -- A VCC = 2.7 V, 160-kHz crystal oscillator (o SUB=oW /2) VCC -- 18 -- A VCC = 2.7 V, 160-kHz crystal oscillator VCC 1.5 -- -- V 396 Values Item Symbol Applicable Pins CLKOUT All output pins except CLKOUT Min -- -- Typ -- -- Max 2.0 0.5 Unit Test Condition mA mA Notes Allow- IOL able output low current (per pin) Allow- IOL able output low current (total) Allow- -I OH able output high current (per pin) All output pins -- -- 20.0 mA CLKOUT SYMCLK, S0 to S7 -- -- -- -- 2.0 0.5 mA mA VCC = 2.5V to 3.6V All output pins except CLKOUT Allow- - IOH able output high All output pins -- -- -- -- 0.2 10.0 mA mA Notes: 1. Applies to the Mask ROM products. 2. Applies to the HD6473937 and HD6473937R. 3. Pin states during current measurement. Pin States during Current Dissipation Measurement Mode Active (high-speed) mode Active (medium- speed) mode Sleep mode Subactive mode Subsleep mode Watch mode RES Pin V CC Internal State Only CPU Operates, decoder stops Other Pins V CC Oscillator Pins System clock oscillator: Crystal Subclock oscillator: PinDX1 = GND V CC V CC V CC V CC Only timers operate, decoder stops Only CPU Operates, decoder stops Only timers operate, CPU and decoder stop Only time base operates, CPU and decoder stop V CC V CC V CC V CC System clock oscillator: Crystal Subclock oscillator: Crystal (However, clock supply to decoder block is stopped) 4. Excludes current in pull-up MOS transistors and output buffers. 397 13.2.3 AC Characteristics Table 13-3 lists the control signal timing, and tables 13-4 list the serial interface timing of the H8/3937 Series and 3937R Series. Table 13-3 Control Signal Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C (including subactive mode) unless otherwise indicated. Applicable Item System clock oscillation frequency Symbol Pins fOSC Min Values Typ -- -- -- -- -- -- Max 10 4 500 500 128 208.3 tOSC s kHz s tW tcyc tsubcyc s ms s ns VCC = 2.7 V to 3.6 V VCC = 1.8 V to 3.6 V s ns VCC = 2.7 V to 3.6 V VCC = 1.8 V to 3.6 V s Figure 13-1 Figure 13-1 VCC = 2.2 V to 3.6 V (In case of Figure 13-8) Figure 13-8 Figure 13-8 Figure 13-1 * ns Unit Test Condition MHz VCC = 2.7 V to 3.6 V VCC = 1.8 V to 3.6 V VCC = 2.7 V to 3.6 V VCC = 1.8 V to 3.6 V Figure 13-1 Reference Figure OSC1, OSC2 2 2 OSC1, OSC2 100 250 OSC clock (o OSC) tOSC cycle time System clock (o) tcyc cycle time Subclock oscilla- fW tion frequency Watch clock (oW ) tW cycle time Subclock (oSUB) cycle time Instruction cycle time Oscillation trc stabilization time tsubcyc DX1, DX 2 DX1, DX 2 2 -- -- -- 2 2 OSC1, OSC2 -- -- DX1, DX 2 -- 40 200 DX1 -- 40 200 DX1 -- 76.8 or -- 160 26.0 or -- 12.5 -- -- 20 -- -- -- -- 8 -- 45 50 2.0 -- -- External clock high width tCPH OSC1 6.51 or -- 3.125 -- -- -- -- External clock low width tCPL OSC1 6.51 or -- 3.125 398 Applicable Item External clock rise time DX1 External clock fall time DX1 Pin RES low width Input pin high width tREL tIH RES tCPf OSC1 Symbol Pins tCPr OSC1 Min -- -- -- -- -- -- 10 Values Typ -- -- -- -- -- -- -- -- Max 10 25 55.0 10 25 55.0 -- -- ns tcyc tcyc tsubcyc ns ns VCC = 2.7 V to 3.6 V VCC = 1.8 V to 3.6 V Unit Test Condition ns VCC = 2.7 V to 3.6 V VCC = 1.8 V to 3.6 V Reference Figure Figure 13-1 Figure 13-1 Figure 13-1 Figure 13-1 Figure 13-2 Figure 13-3 IRQ1 to 2 IRQ4, WKP 0 to WKP 7, ADTRG, TMIC TMIF, TMIG IRQ1 to 2 IRQ4, WKP 0 to WKP 7, ADTRG, TMIC, TMIF, TMIG UD 4 Input pin low width tIL -- -- tcyc tsubcyc Figure 13-3 UD pin minimum tUDH modulation width tUDL -- -- tcyc tsubcyc Figure 13-4 Note: * Selected with SA1 and SA0 of system clock control register 2 (SYSCR2). 399 Table 13-4 Serial Interface (SCI31, SCI32) Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C (including subactive mode) unless otherwise indicated. Values Item Input clock cycle Symbol Min Asynchronous tScyc Synchronous tSCKW tTXD tRXS tRXH 4 6 0.4 -- Typ -- -- -- -- Max -- -- 0.6 1 -- -- Unit tcyc or tsubcyc tScyc tcyc or tsubcyc ns ns Figure 13-5 Figure 13-6 Figure 13-6 Figure 13-6 Test Conditions Reference Figure Figure 13-5 Input clock pulse width Transmit data delay time(synchronous) Receive data setup time (synchronous) Receive data hold time (synchronous) 400.0 -- 400.0 -- 400 13.2.4 A/D Converter Characteristics Table 13-5 shows the A/D converter characteristics of the H8/3937 Series and H8/3937R Series. Table 13-5 A/D Converter Characteristics VCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C (including subactive mode) unless otherwise indicated. Item Analog power supply voltage Analog input voltage Analog power supply current Applicable Symbol Pins AV CC AV CC AV IN AI OPE AI STOP1 AN0 to AN7 AV CC AV CC Min 1.8 - 0.3 -- -- Values Typ Max -- 3.6 -- -- 600 Unit V Test Condition Notes *1 AV CC + 0.3 V 1.0 -- mA A AV CC = 3.0 V *2 Reference value *3 Analog input capacitance Allowable signal source impedance Resolution (data length) Nonlinearity error AI STOP2 CAIN RAIN AV CC AN0 to AN7 -- -- -- -- -- -- 5 15.0 10.0 A pF k -- -- -- -- -- -- -- -- 12.4 62 -- -- -- -- -- -- -- -- -- -- 10 2.5 5.5 7.5 0.5 3.0 6.0 8.0 124 124 bit LSB AV CC = 3.0 to 3.6 V VCC = 3.0 to 3.6 V AV CC = 2.0 to 3.6 V VCC = 2.0 to 3.6 V Except the above *4 Quantization error Absolute accuracy LSB LSB AV CC = 3.0 to 3.6 V VCC = 3.0 to 3.6 V AV CC = 2.0 to 3.6 V VCC = 2.0 to 3.6 V Except the above AV CC = 2.7 to 3.6 V VCC = 2.7 to 3.6 V Except the above *4 Conversion time s Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AI STOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AI STOP2 is the current at reset and in standby, watch, subactive, and subsleep modes while the A/D converter is idle. 4. Conversion time: 62 s 401 13.3 Operation Timing Figures 13-1 to 13-7 show timing diagrams. t OSC , tw VIH OSC1 Dx1 VIL t CPH t CPr t CPL t CPf Figure 13-1 Clock Input Timing RES VIL tREL Figure 13-2 RES Low Width IRQ1 to IRQ4, WKP0 to WKP7, ADTRG, TMIC, TMIF, TMIG VIH VIL t IL t IH Figure 13-3 Input Timing 402 VIH UD VIL t UDL t UDH Figure 13-4 UD Pin Minimum Modulation Width Timing t SCKW SCK 31 SCK 32 t scyc Figure 13-5 SCK3 Input Clock Timing 403 t scyc SCK 31 VIH or VOH * SCK 32 VIL or VOL * t TXD TXD31 TXD32 (transmit data) VOH VOL * * t RXS t RXH RXD31 RXD32 (receive data) Note: * Output timing reference levels Output high Output low VOH = 1/2 VCC + 0.2 V VOL = 0.8 V Load conditions are shown in figure 13-7. Figure 13-6 SCI3 Synchronous Mode Input/Output Timing 404 13.4 Output Load Circuit VCC 2.4 k Output pin 30 pF 12 k Figure 13-7 Output Load Condition 13.5 Resonator Equivalent Circuit LS CS RS OSC1 CO OSC2 Crystal Resonator Parameter Frequency (MHz) RS (max) CO (max) 4.193 100 16 pF Ceramic Resonator Parameters Frequency (MHz) RS (max) CO (max) 4 8.8 36 pF Figure 13-8 Resonator Equivalent Circuit 405 13.6 Usage Note The ZTAT and mask ROM versions both satisfy the electrical characteristics shown in this manual, but actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns, and so on. When system evaluation testing is carried out using the ZTAT version, the same evaluation testing should also be conducted for the mask ROM version when changing over to that version. 406 Appendix A CPU Instruction Set A.1 Instructions Operation Notation Rd8/16 Rs8/16 Rn8/16 CCR N Z V C PC SP #xx: 3/8/16 d: 8/16 @aa: 8/16 + - x / -- General register (destination) (8 or 16 bits) General register (source) (8 or 16 bits) General register (8 or 16 bits) Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data (3, 8, or 16 bits) Displacement (8 or 16 bits) Absolute address (8 or 16 bits) Addition Subtraction Multiplication Division Logical AND Logical OR Exclusive logical OR Move Logical complement Condition Code Notation Symbol * 0 -- Modified according to the instruction result Not fixed (value not guaranteed) Always cleared to 0 Not affected by the instruction execution result 407 Table A-1 lists the H8/300L CPU instruction set. Table A-1 Instruction Set Addressing Mode/ Instruction Length (bytes) Condition Code Operand Size @-Rn/@Rn+ @(d:8, PC) No. of States @(d:16, Rn) @aa: 8/16 #xx: 8/16 Mnemonic MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd MOV.B @(d:16, Rs), Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd MOV.W @(d:16, Rs), Rd MOV.W @Rs+, Rd MOV.W @aa:16, Rd MOV.W Rs, @Rd MOV.W Rs, @(d:16, Rd) MOV.W Rs, @-Rd MOV.W Rs, @aa:16 POP Rd PUSH Rs Operation Rn @Rn Implied @@aa I HNZVC B #xx:8 Rd8 B Rs8 Rd8 B @Rs16 Rd8 B @(d:16, Rs16) Rd8 B @Rs16 Rd8 Rs16+1 Rs16 B @aa:8 Rd8 B @aa:16 Rd8 B Rs8 @Rd16 B Rs8 @(d:16, Rd16) B Rd16-1 Rd16 Rs8 @Rd16 B Rs8 @aa:8 B Rs8 @aa:16 W #xx:16 Rd W Rs16 Rd16 W @Rs16 Rd16 W @(d:16, Rs16) Rd16 W @Rs16 Rd16 Rs16+2 Rs16 W @aa:16 Rd16 W Rs16 @Rd16 W Rs16 @(d:16, Rd16) W Rd16-2 Rd16 Rs16 @Rd16 W Rs16 @aa:16 W @SP Rd16 SP+2 SP W SP-2 SP Rs16 @SP 2 2 2 4 2 2 4 2 4 2 2 4 4 2 2 4 2 4 2 4 2 4 2 2 ---- 0 --2 ---- 0 --2 ---- 0 --4 ---- 0 --6 ---- 0 --6 ---- 0 --4 ---- 0 --6 ---- 0 --4 ---- 0 --6 ---- 0 --6 ---- 0 --4 ---- 0 --6 ---- 0 --4 ---- 0 --2 ---- 0 --4 ---- 0 --6 ---- 0 --6 ---- 0 --6 ---- 0 --4 ---- 0 --6 ---- 0 --6 ---- 0 --6 ---- 0 --6 ---- 0 --6 408 Addressing Mode/ Instruction Length (bytes) Condition Code Operand Size @-Rn/@Rn+ @(d:8, PC) No. of States @(d:16, Rn) @aa: 8/16 #xx: 8/16 Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS.W #1, Rd ADDS.W #2, Rd INC.B Rd DAA.B Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS.W #1, Rd SUBS.W #2, Rd DEC.B Rd DAS.B Rd NEG.B Rd CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W Rs, Rd MULXU.B Rs, Rd DIVXU.B Rs, Rd Operation Rn @Rn Implied @@aa I H N Z VC B Rd8+#xx:8 Rd8 B Rd8+Rs8 Rd8 W Rd16+Rs16 Rd16 B Rd8+#xx:8 +C Rd8 B Rd8+Rs8 +C Rd8 W Rd16+1 Rd16 W Rd16+2 Rd16 B Rd8+1 Rd8 B Rd8 decimal adjust Rd8 B Rd8-Rs8 Rd8 W Rd16-Rs16 Rd16 B Rd8-#xx:8 -C Rd8 B Rd8-Rs8 -C Rd8 W Rd16-1 Rd16 W Rd16-2 Rd16 B Rd8-1 Rd8 B Rd8 decimal adjust Rd8 B 0-Rd Rd B Rd8-#xx:8 B Rd8-Rs8 W Rd16-Rs16 B Rd8 x Rs8 Rd16 B Rd16/Rs8 Rd16 (RdH: remainder, RdL: quotient) B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd Rd 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -- -- -- (1) -- -- 2 2 2 (2) 2 (2) 2 -- -- -- -- ---- 2 -- -- -- -- ---- 2 ---- --* -- -- (1) -- -- --2 * (3) 2 2 2 (2) 2 (2) 2 -- -- -- -- ---- 2 -- -- -- -- ---- 2 ---- --* -- -- -- -- (1) --2 * --2 2 2 2 2 -- -- -- -- -- -- 14 -- -- (5) (6) -- -- 14 AND.B #xx:8, Rd AND.B Rs, Rd OR.B #xx:8, Rd OR.B Rs, Rd XOR.B #xx:8, Rd XOR.B Rs, Rd NOT.B Rd 2 2 2 2 2 2 2 ---- ---- ---- ---- ---- ---- ---- 0 --2 0 --2 0 --2 0 --2 0 --2 0 --2 0 --2 409 Addressing Mode/ Instruction Length (bytes) Condition Code Operand Size @-Rn/@Rn+ @(d:8, PC) No. of States @(d:16, Rn) @aa: 8/16 #xx: 8/16 Mnemonic SHAL.B Rd Operation C b7 b0 C b7 b0 0 b7 b0 C b7 b0 0 Rn @Rn Implied @@aa I HNZVC B 2 ---- 2 SHAR.B Rd B 2 ---- 0 2 SHLL.B Rd B C 2 ---- 0 2 SHLR.B Rd B 0 2 ---- 0 0 2 ROTXL.B Rd B C b7 b0 2 ---- 0 2 ROTXR.B Rd B b7 b0 C 2 ---- 0 2 ROTL.B Rd B C b7 b0 C b7 b0 2 ---- 0 2 ROTR.B Rd B 2 ---- 0 2 BSET #xx:3, Rd BSET #xx:3, @Rd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @Rd BSET Rn, @aa:8 BCLR #xx:3, Rd BCLR #xx:3, @Rd BCLR #xx:3, @aa:8 BCLR Rn, Rd B (#xx:3 of Rd8) 1 B (#xx:3 of @Rd16) 1 B (#xx:3 of @aa:8) 1 B (Rn8 of Rd8) 1 B (Rn8 of @Rd16) 1 B (Rn8 of @aa:8) 1 B (#xx:3 of Rd8) 0 B (#xx:3 of @Rd16) 0 B (#xx:3 of @aa:8) 0 B (Rn8 of Rd8) 0 2 4 4 2 4 4 2 4 4 2 ---- ------ --2 ---- ------ --8 ---- ------ --8 ---- ------ --2 ---- ------ --8 ---- ------ --8 ---- ------ --2 ---- ------ --8 ---- ------ --8 ---- ------ --2 410 Addressing Mode/ Instruction Length (bytes) Condition Code Operand Size @-Rn/@Rn+ @(d:8, PC) No. of States @(d:16, Rn) @aa: 8/16 #xx: 8/16 Mnemonic BCLR Rn, @Rd BCLR Rn, @aa:8 BNOT #xx:3, Rd BNOT #xx:3, @Rd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 Operation Rn @Rn Implied @@aa I HNZVC B (Rn8 of @Rd16) 0 B (Rn8 of @aa:8) 0 B (#xx:3 of Rd8) (#xx:3 of Rd8) B (#xx:3 of @Rd16) (#xx:3 of @Rd16) B (#xx:3 of @aa:8) (#xx:3 of @aa:8) B (Rn8 of Rd8) (Rn8 of Rd8) B (Rn8 of @Rd16) (Rn8 of @Rd16) B (Rn8 of @aa:8) (Rn8 of @aa:8) B (#xx:3 of Rd8) Z B (#xx:3 of @Rd16) Z B (#xx:3 of @aa:8) Z B (Rn8 of Rd8) Z B (Rn8 of @Rd16) Z B (Rn8 of @aa:8) Z B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C 2 2 2 2 2 2 2 2 2 4 4 ---- ------ --8 ---- ------ --8 ---- ------ --2 4 4 ---- ------ --8 ---- ------ --8 ---- ------ --2 4 4 ---- ------ --8 ---- ------ --8 ---- -- -- --2 4 4 ---- -- -- --6 ---- -- -- --6 ---- -- -- --2 ---- -- -- --6 4 ---- -- -- --6 ---- ------ 2 ---- ------ 6 4 ---- ------ 6 ---- ------ 2 ---- ------ 6 4 ---- ------ 6 ---- ------ --2 ---- ------ --8 4 ---- ------ --8 ---- ------ --2 4 4 4 4 4 4 ---- ------ --8 ---- ------ --8 ---- ------ 2 ---- ------ 6 4 ---- ------ 6 4 411 Addressing Mode/ Instruction Length (bytes) Condition Code Operand Size @-Rn/@Rn+ @(d:8, PC) No. of States @(d:16, Rn) @aa: 8/16 #xx: 8/16 Mnemonic BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 BIXOR #xx:3, Rd BIXOR #xx:3, @Rd BIXOR #xx:3, @aa:8 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 Operation Rn @Rn Implied @@aa I HNZVC B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C -- PC PC+d:8 -- PC PC+2 -- If condition -- is true then CZ=0 CZ=1 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV = 0 NV = 1 Z (NV) = 0 Z (NV) = 1 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ---- ------ 2 ---- ------ 6 ---- ------ 6 ---- ------ 2 ---- ------ 6 ---- ------ 6 ---- ------ 2 ---- ------ 6 ---- ------ 6 ---- ------ 2 ---- ------ 6 ---- ------ 6 ---- ------ 2 ---- ------ 6 ---- ------ 6 ---- ------ --4 ---- ------ --4 ---- ------ --4 ---- ------ --4 ---- ------ --4 ---- ------ --4 ---- ------ --4 ---- ------ --4 ---- ------ --4 ---- ------ --4 ---- ------ --4 ---- ------ --4 ---- ------ --4 ---- ------ --4 ---- ------ --4 ---- ------ --4 -- PC PC+d:8 C = 0 -- else next; -- -- -- -- -- -- -- -- -- -- 412 Addressing Mode/ Instruction Length (bytes) Condition Code Operand Size @-Rn/@Rn+ @(d:8, PC) No. of States @(d:16, Rn) @aa: 8/16 #xx: 8/16 Mnemonic JMP @Rn JMP @aa:16 JMP @@aa:8 BSR d:8 Operation Rn @Rn Implied @@aa I HNZVC -- PC Rn16 -- PC aa:16 -- PC @aa:8 -- SP-2 SP PC @SP PC PC+d:8 -- SP-2 SP PC @SP PC Rn16 -- SP-2 SP PC @SP PC aa:16 SP-2 SP PC @SP PC @aa:8 -- PC @SP SP+2 SP -- CCR @SP SP+2 SP PC @SP SP+2 SP -- Transit to sleep mode. B #xx:8 CCR B Rs8 CCR B CCR Rd8 B CCR#xx:8 CCR B CCR#xx:8 CCR B CCR#xx:8 CCR -- PC PC+2 -- if R4L0 Repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L Until R4L=0 else next; 2 2 2 2 2 2 2 4 2 2 ---- ------ --4 ---- ------ --6 ---- ------ --8 ---- ------ --6 JSR @Rn 2 ---- ------ --6 JSR @aa:16 4 ---- ------ --8 JSR @@aa:8 2 ---- ------ --8 RTS RTE 2 ---- ------ --8 2 10 SLEEP LDC #xx:8, CCR LDC Rs, CCR STC CCR, Rd ANDC #xx:8, CCR ORC #xx:8, CCR XORC #xx:8, CCR NOP EEPMOV 2 ---- ------ --2 2 2 ---- ------ --2 2 2 2 2 ---- ------ --2 4 -- -- -- -- -- -- (4) 413 Notes: (1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. (2) If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. (3) Set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation. (4) The number of states required for execution is 4n + 9 (n = value of R4L). (5) Set to 1 if the divisor is negative; otherwise cleared to 0. (6) Set to 1 if the divisor is zero; otherwise cleared to 0. 414 A.2 Operation Code Map Table A-2 is an operation code map. It shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1. 415 ; ; ; ;; ; 2 ADD SUB DEC SUBS CMP SUBX INC ADDS MOV ADDX DAA DAS 3 4 5 6 7 8 9 A B C D E F 416 BVS JMP MOV * MOV EEPMOV Bit-manipulation instructions BPL BMI BGE BLT BGT JSR BLE Low High 0 1 Table A-2 0 NOP SLEEP STC LDC ORC XORC ANDC LDC SHLL SHLR ROTXL ROTXR NOT 1 OR XOR AND SHAL SHAR ROTL ROTR NEG 2 MOV 3 4 BRA BRN BHI BLS BCC BCS BNE BEQ BVC 5 MULXU DIVXU RTS BSR RTE Operation Code Map BST 6 BSET BNOT BCLR BTST BOR BXOR BAND BIST BLD 7 BIOR BIXOR BIAND BILD 8 ADD 9 ADDX A CMP B SUBX C OR D XOR E AND F MOV Note: * The PUSH and POP instructions are identical in machine language to MOV instructions. A.3 Number of Execution States The tables here can be used to calculate the number of states required for instruction execution. Table A-4 indicates the number of states required for each cycle (instruction fetch, read/write, etc.), and table A-3 indicates the number of cycles of each type occurring in each instruction. The total number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I x SI + J x SJ + K x SK + L x SL+ M x SM + N x SN Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed. BSET #0, @FF00 From table A-4: I = L = 2, J = K = M = N= 0 From table A-3: S I = 2, SL = 2 Number of states required for execution = 2 x 2 + 2 x 2 = 8 When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and on-chip RAM is used for stack area. JSR @@ 30 From table A-4: I = 2, J = K = 1, L = M = N = 0 From table A-3: S I = SJ = SK = 2 Number of states required for execution = 2 x 2 + 1 x 2+ 1 x 2 = 8 Table A-3 Number of Cycles in Each Instruction Access Location On-Chip Memory SI SJ SK SL SM SN 1 2 or 3* -- 1 2 On-Chip Peripheral Module -- Execution Status (instruction cycle) Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation Note: * Depends on which on-chip module is accessed. See 2.9.1, Notes on Data Access for details. 417 Table A-4 Instruction ADD Number of Cycles in Each Instruction Instruction Fetch I 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 2 2 2 2 1 1 Branch Stack Byte Data Word Data Internal Addr. Read Operation Access Access Operation J K L M N Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDX AND ANDC BAND ADDS.W #1, Rd ADDS.W #2, Rd ADDX.B #xx:8, Rd ADDX.B Rs, Rd AND.B #xx:8, Rd AND.B Rs, Rd ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BCLR BCLR #xx:3, Rd BCLR #xx:3, @Rd BCLR #xx:3, @aa: 8 BCLR Rn, Rd BCLR Rn, @Rd BCLR Rn, @aa:8 418 Instruction BIAND Mnemonic BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 Instruction Fetch I 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 Branch Stack Byte Data Word Data Internal Addr. Read Operation Access Access Operation J K L M N 1 1 1 1 1 1 2 2 1 1 1 1 2 2 2 2 1 1 2 2 2 2 1 2 2 BILD BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @Rd BIXOR #xx:3, @aa:8 BLD BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @Rd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BSET BSET #xx:3, Rd BSET #xx:3, @Rd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @Rd BSET Rn, @aa:8 BSR BST BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 419 Instruction BTST Mnemonic BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 Instruction Fetch I 1 2 2 1 2 2 1 2 2 1 1 1 1 1 1 1 2 1 2 2 2 2 2 2 1 1 1 1 1 2 1 1 2 1 Branch Stack Byte Data Word Data Internal Addr. Read Operation Access Access Operation J K L M N 1 1 1 1 1 1 BXOR BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 CMP CMP. B #xx:8, Rd CMP. B Rs, Rd CMP.W Rs, Rd DAA DAS DEC DIVXU EEPMOV INC JMP DAA.B Rd DAS.B Rd DEC.B Rd DIVXU.B Rs, Rd EEPMOV INC.B Rd JMP @Rn JMP @aa:16 JMP @@aa:8 12 2n+2* 1 2 1 1 1 1 1 2 2 JSR JSR @Rn JSR @aa:16 JSR @@aa:8 LDC MOV LDC #xx:8, CCR LDC Rs, CCR MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd MOV.B @(d:16, Rs), Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd 1 1 1 1 1 1 2 Note: * n: Initial value in R4L. The source and destination operands are accessed n + 1 times each. 420 Instruction MOV Mnemonic MOV.B Rs, @(d:16, Rd) MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd MOV.W @(d:16, Rs), Rd MOV.W @Rs+, Rd MOV.W @aa:16, Rd MOV.W Rs, @Rd MOV.W Rs, @(d:16, Rd) MOV.W Rs, @-Rd MOV.W Rs, @aa:16 Instruction Fetch I 2 1 1 2 2 1 1 2 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 Branch Stack Byte Data Word Data Internal Addr. Read Operation Access Access Operation J K L M N 1 1 1 1 2 1 1 1 1 1 1 1 1 12 2 2 MULXU NEG NOP NOT OR ORC ROTL ROTR ROTXL ROTXR RTE RTS SHAL SHAR SHLL SHLR SLEEP STC MULXU.B Rs, Rd NEG.B Rd NOP NOT.B Rd OR.B #xx:8, Rd OR.B Rs, Rd ORC #xx:8, CCR ROTL.B Rd ROTR.B Rd ROTXL.B Rd ROTXR.B Rd RTE RTS SHAL.B Rd SHAR.B Rd SHLL.B Rd SHLR.B Rd SLEEP STC CCR, Rd 2 1 2 2 421 Instruction SUB SUB SUBS POP PUSH SUBX XOR XORC Mnemonic SUB.B Rs, Rd SUB.W Rs, Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBS.W #1, Rd SUBS.W #2, Rd POP Rd PUSH Rs SUBX.B #xx:8, Rd SUBX.B Rs, Rd XOR.B #xx:8, Rd XOR.B Rs, Rd XORC #xx:8, CCR Instruction Fetch I 1 1 1 1 1 1 1 1 1 1 1 1 1 Branch Stack Byte Data Word Data Internal Addr. Read Operation Access Access Operation J K L M N 1 1 2 2 422 Appendix B Internal I/O Registers B.1 Lower Address H'90 H'91 H'92 H'93 H'94 H'95 H'96 H'97 H'98 H'99 H'9A H'9B H'9C H'9D H'9E H'9F H'A0 H'A1 H'A2 H'A3 H'A4 H'A5 H'A6 H'A7 H'A8 H'A9 H'AA H'AB H'AC H'AD H'AE H'AF H'B0 H'B1 TMA TCA TMA7 TCA7 TMA6 TCA6 TMA5 TCA5 -- TCA4 TMA3 TCA3 TMA2 TCA2 TMA1 TCA1 TMA0 TCA0 Timer A SMR32 BRR32 SCR32 TDR32 SSR32 RDR32 COM32 BRR327 TIE32 TDR327 TDRE32 RDR327 CHR32 BRR326 RIE32 TDR326 RDRF32 RDR326 PE32 BRR325 TE32 TDR325 OER32 RDR325 PM32 BRR324 RE32 TDR324 FER32 RDR324 STOP32 BR323 MPIE32 TDR323 PER32 RDR323 MP32 BRR322 TEIE32 TDR322 TEND32 RDR322 CKS321 BRR321 CKE321 TDR321 MPBR32 RDR321 CKS320 BRR320 CKE320 TDR320 MPBT32 RDR320 SCI32 SCR1 SCSR1 SDRU SDRL SNC1 -- SDRU7 SDRL7 SNC0 SOL SDRU6 SDRL6 MRKON ORER SDRU5 SDRL5 LTCH -- SDRU4 SDRL4 CKS3 -- SDRU3 SDRL3 CKS2 -- SDRU2 SDRL2 CKS1 MTRF SDRU1 SDRL1 CKS0 STF SDRU0 SDRL0 SCI1 SMR31 BRR31 SCR31 TDR31 SSR31 RDR31 COM31 BRR317 TIE31 TDR317 TDRE31 RDR317 CHR31 BRR316 RIE31 TDR316 RDRF31 RDR316 PE31 BRR315 TE31 TDR315 OER31 RDR315 PM31 BRR314 RE31 TDR314 FER31 RDR314 STOP31 BRR313 MPIE31 TDR313 PER31 RDR313 MP31 BRR312 TEIE31 TDR312 TEND31 RDR312 CKS311 BRR311 CKE31 TDR311 MPBR31 RDR311 CKS310 BRR310 CKE310 TDR310 MPBT31 RDR310 SCI31 Addresses Register Name WEGR SPCR CWOSR Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 System control -- -- -- -- SPC32 -- SPC31 -- SCINV3 -- SCINV2 -- SCINV1 -- SCINV0 CWOS SCI Timer A 423 Lower Address H'B2 H'B3 H'B4 H'B5 H'B6 H'B7 H'B8 H'B9 H'BA H'BB H'BC H'BD H'BE H'BF H'C0 H'C1 H'C2 H'C3 H'C4 H'C5 H'C6 H'C7 H'C8 H'C9 H'CA H'CB H'CC H'CD H'CE H'CF H'D0 H'D1 H'D2 H'D3 H'D4 H'D5 H'D6 H'D7 H'D8 Register Name TCSRW TCW TMC TCC/ TLC TCRF TCSRF TCFH TCFL OCRFH OCRFL TMG ICRGF ICRGR Bit Names Bit 7 B6WI TCW7 TMC7 TCC/ TLC7 TOLH OVFH TCFH7 TCFL7 Bit 6 TCWE TCW6 TMC6 TCC6/ TLC6 CKSH2 CMFH TCFH6 TCFL6 Bit 5 B4WI TCW5 TMC5 TCC5/ TLC5 CKSH1 OVIEH TCFH5 TCFL5 Bit 4 Bit 3 Bit 2 WDON TCW2 TMC2 TCC2/ TLC2 CKSL2 CMFL TCFH2 TCFL2 Bit 1 BOW1 TCW1 TMC1 TCC1/ TLC1 CKSL1 OVIEL TCFH1 TCFL1 Bit 0 WRST TCWO TMC0 TCC0/ TLC0 CKSL0 CCLRL TCFH0 TCFL0 OCRFH0 OCRFL0 CKS0 ICRGFO ICRGRO Module Name Watchdog timer Timer C TCSRWE B2WI TCW4 -- TCC4/ TLC4 CKSH0 CCLRH TCFH4 TCFL4 TCW3 -- TCC3/ TLC3 TOLL OVFL TCFH3 TCFL3 Timer F OCRFH7 OCRFH6 OCRFL7 OVFH ICRGF7 ICRGR7 OCRFL6 OVFL ICRGF6 ICRGR6 OCRFH5 OCRFH4 OCRFH3 OCRFL5 OVIE ICRGF5 ICRGR5 OCRFL4 IIEGS ICRGF4 ICRGR4 OCRFL3 CCLR1 ICRGF3 ICRGR3 OCRFH2 OCRFH1 OCRFL2 CCLR0 ICRGF2 ICRGR2 OCRFL1 CKS1 ICRGF1 ICRGR1 Timer G ADRRH ADRRL AMR ADSR PMR1 PMR2 PMR3 PMR4 PMR5 ADR9 ADR1 CKS ADSF IRQ3 -- -- NMOD7 WKP7 ADR8 ADR0 TRGE -- IRQ2 -- -- NMOD6 WKP6 ADR7 -- -- -- IRQ1 POF1 WDCKS NMOD5 WKP5 ADR6 -- -- -- IRQ4 -- NCS NMOD4 WKP4 ADR5 -- CH3 -- TMIG -- IRQ0 NMOD3 WKP3 ADR4 -- CH2 -- TMOFH SO1 RESO NMOD2 WKP2 ADR3 -- CH1 -- TMOFL SI1 UD NMOD1 WKP1 ADR2 -- CH0 -- TMOW SCK1 -- NMOD0 WKP0 A/D converter I/O port PDR1 PDR2 PDR3 PDR4 PDR5 P1 7 -- P3 7 -- P5 7 P1 6 -- P3 6 -- P5 6 P1 5 -- P3 5 -- P5 5 P1 4 P2 4 P3 4 -- P5 4 P1 3 P2 3 P3 3 P4 3 P5 3 P1 2 P2 2 P3 2 P4 2 P5 2 P1 1 P2 1 P3 1 P4 1 P5 1 P1 0 P2 0 P3 0 P4 0 P5 0 I/O Port 424 Lower Address H'D9 H'DA H'DB H'DC H'DD H'DE H'DF H'E0 H'E1 H'E2 H'E3 H'E4 H'E5 H'E6 H'E7 H'E8 H'E9 H'EA H'EB H'EC H'ED H'EE H'EF H'F0 H'F1 H'F2 H'F3 H'F4 H'F5 H'F6 H'F7 H'F8 H'F9 H'FA H'FB H'FC H'FD H'FE H'FF Register Name PDR6 PDR7 PDR8 PDR9 PDRA PDRB Bit Names Bit 7 P6 7 P7 7 P8 7 -- -- PB7 Bit 6 P6 6 P7 6 P8 6 -- -- PB6 Bit 5 P6 5 P7 5 P8 5 -- -- PB5 Bit 4 P6 4 P7 4 P8 4 -- -- PB4 Bit 3 P6 3 P7 3 P8 3 P9 3 PA3 PB3 Bit 2 P6 2 P7 2 P8 2 P9 2 PA2 PB2 Bit 1 P6 1 P7 1 P8 1 P9 1 PA1 PB1 Bit 0 P6 0 P7 0 P8 0 P9 0 PA0 PB0 Module Name I/O Port PUCR1 PUCR3 PUCR5 PUCR6 PCR1 PCR2 PCR3 PCR4 PCR5 PCR6 PCR7 PCR8 PCR9 PCRA PUCR1 7 PUCR3 7 PUCR5 7 PUCR6 7 PCR1 7 -- PCR3 7 -- PCR5 7 PCR6 7 PCR7 7 PCR8 7 -- -- PUCR1 6 PUCR3 6 PUCR5 6 PUCR6 6 PCR1 6 -- PCR3 6 -- PCR5 6 PCR6 6 PCR7 6 PCR8 6 -- -- PUCR1 5 PUCR3 5 PUCR5 5 PUCR6 5 PCR1 5 -- PCR3 5 -- PCR5 5 PCR6 5 PCR7 5 PCR8 5 -- -- PUCR1 4 PUCR3 4 PUCR5 4 PUCR6 4 PCR1 4 PCR2 4 PCR3 4 -- PCR5 4 PCR6 4 PCR7 4 PCR8 4 -- -- PUCR1 3 PUCR3 3 PUCR5 3 PUCR6 3 PCR1 3 PCR2 3 PCR3 3 -- PCR5 3 PCR6 3 PCR7 3 PCR8 3 PCR9 3 PCRA3 PUCR1 2 PUCR3 2 PUCR5 2 PUCR6 2 PCR1 2 PCR2 2 PCR3 2 PCR4 2 PCR5 2 PCR6 2 PCR7 2 PCR8 2 PCR9 2 PCRA2 PUCR1 1 PUCR3 1 PUCR5 1 PUCR6 1 PCR1 1 PCR2 1 PCR3 1 PCR4 1 PCR5 1 PCR6 1 PCR7 1 PCR8 1 PCR9 1 PCRA1 PUCR1 0 PUCR3 0 PUCR5 0 PUCR6 0 PCR1 0 PCR2 0 PCR3 0 PCR4 0 PCR5 0 PCR6 0 PCR7 0 PCR8 0 PCR9 0 PCRA0 I/O Port SYSCR1 SYSCR2 IEGR IENR1 IENR2 SSBY -- -- IENTA IENDT STS2 -- -- IENS1 IENAD STS1 -- -- IENWP -- STS0 NESEL IEG4 IEN4 IENTG LSON DTON IEG3 IEN3 IENTFH -- MSON IEG2 IEN2 IENTFL MA1 SA1 IEG1 IEN1 IENTC MA0 SA0 IEG0 IEN0 -- System control IRR1 IRRI2 IRRTA IRRDT IRRS1 IRRAD -- -- IRRI4 IRRTG IRRI3 IRRTFH IRRI2 IRRTFL IRRI1 IRRTC IRRI0 -- IWPR IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 CK STP R1 S1CKSTP S31CKSTP S32CKSTP A DCK S TP TGCK S TP TFCKSTP TCCK S TP TA CK S TP CK STP R2 -- -- -- -- -- WDCKSTP -- -- Legend SCI: Serial Communication Interface 425 B.2 Functions Register name Address to which the register is mapped Name of on-chip supporting module Timer C Register acronym TMC--Timer mode register C H'B4 Bit numbers Bit 7 TMC7 Initial value Read/Write 0 R/W 6 TMC6 0 R/W 5 TMC5 0 R/W 4 -- 1 -- 3 -- 1 -- 2 TMC2 0 R/W 1 TMC1 0 R/W 0 TMC0 0 R/W Initial bit values Names of the bits. Dashes (--) indicate reserved bits. Possible types of access R W Read only Write only R/W Read and write Clock select 0 0 0 Internal clock: o/8192 1 Internal clock: o/2048 1 0 Internal clock: o/512 1 Internal clock: o/64 1 0 0 Internal clock: o/16 1 Internal clock: o/4 1 0 Internal clock: o W /4 1 External event (TMIC): Rising or falling edge Counter up/down control 0 0 TCC is an up-counter 1 TCC is a down-counter 1 * TCC up/down control is determined by input at pin UD. TCC is a down-counter if the UD input is high, and an up-counter if the UD input is low. Auto-reload function select 0 Interval timer function selected 1 Auto-reload function selected *: Don't care Full name of bit Descriptions of bit settings 426 WEGR--Wakeup Edge Select Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'90 2 0 R/W 1 0 R/W System control 0 0 R/W WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 WKPn edge selected 0 1 WKPn pin falling edge detected WKPn pin rising edge detected (n = 0 to 7) SPCR--Serial Port Control Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 SPC32 0 R/W 4 SPC31 0 R/W 3 0 R/W H'91 2 0 R/W 1 0 R/W 0 0 R/W SCI SCINV3 SCINV2 SCINV1 SCINV0 RXD31 pin input data inversion switch 0 1 RXD31 input data is not inverted RXD31 input data is inverted TXD31 pin output data inversion switch 0 1 TXD31 output data is not inverted TXD31 output data is inverted RXD32 pin input data inversion switch 0 1 RXD32 input data is not inverted RXD32 input data is inverted TXD32 pin output data inversion switch 0 1 TXD32 output data is not inverted TXD32 output data is inverted P35TXD31 pin function switch 0 1 Functions as P35 I/O pin Functions as TXD31 output pin P42/TXD32pin function switch 0 1 Function as P42 I/O pin Function as TXD32 output pin 427 CWOSR--Subclock Output Select Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- H'92 2 -- 1 -- 1 -- 1 -- Timer A 0 CWOS 0 R/W TMOW pin clock select 0 1 Clock output from TMA is output oW is output 428 SMR31--Serial mode register 31 Bit Initial value Read/Write 7 COM31 0 R/W 6 CHR31 0 R/W 5 PE31 0 R/W 4 PM31 0 R/W 3 STOP31 0 R/W H'98 2 MP31 0 R/W 1 0 R/W SCI31 0 0 R/W CKS311 CKS310 Clock select 0 0 o clock 0 1 ow/2 clock/ow clock 1 0 o/16 clock 1 1 o/64 clock Multiprocessor mode 0 Multiprocessor communication function disabled 1 Multiprocessor communication function enabled Stop bit length 0 1 stop bit 1 2 stop bits Parity mode 0 Even parity 1 Odd parity Parity enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled Character length 0 8-bit data/5-bit data 1 7-bit data/5-bit data Communication mode 0 Asynchronous mode 1 Synchronous mode 429 BRR31--Bit rate register31 Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'99 2 1 R/W 1 1 R/W SCI31 0 1 R/W BRR317 BRR316 BRR315 BRR314 BRR313 BRR312 BRR311 BRR310 Serial transmit/receive bit rate setting 430 SCR31--Serial control register 31 Bit Initial value Read/Write 7 TIE31 0 R/W 6 RIE31 0 R/W 5 TE31 0 R/W 4 RE31 0 R/W 3 0 R/W H'9A 2 0 R/W 1 0 R/W SCI31 0 0 R/W MPIE31 TEIE31 CKE311 CKE310 Clock enable Bit 0 Bit 1 CKE311 CKE310 Communication Mode Asynchronous 0 0 Synchronous Asynchronous 1 0 Synchronous Asynchronous 0 1 Synchronous Asynchronous 1 1 Synchronous Transmit end interrupt enable 0 1 Transmit end interrupt request (TEI) disabled Transmit end interrupt request (TEI) enabled Description Clock Source SCK 3 Pin Function I/O port Internal clock Serial clock output Internal clock Clock output Internal clock Reserved (Do not specify this combination) Clock input External clock Serial clock input External clock Reserved (Do not specify this combination) Reserved (Do not specify this combination) Multiprocessor interrupt enable 0 Multiprocessor interrupt request disabled (normal receive operation) [Clearing conditions] When data is received in which the multiprocessor bit is set to 1 Multiprocessor interrupt request enabled The receive interrupt request (RXI), receive error interrupt request (ERI), and setting of the RDRF, FER, and OER flags in the serial status register (SSR), are disabled until data with the multiprocessor bit set to 1 is received. 1 Receive enable 0 1 Receive operation disabled (RXD pin is I/O port) Receive operation enabled (RXD pin is receive data pin) Transmit enable 0 1 Transmit operation disabled (TXD pin is transmit data pin) Transmit operation enabled (TXD pin is transmit data pin) Receive interrupt enable 0 1 Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled Transmit interrupt enable 0 Transmit data empty interrupt request (TXI) disabled 1 Transmit data empty interrupt request (TXI) enabled 431 TDR31--Transmit data register 31 Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'9B 2 1 R/W 1 1 R/W SCI31 0 1 R/W TDR317 TDR316 TDR315 TDR314 TDR313 TDR312 TDR311 TDR310 Data for transfer to TSR 432 SSR31--Serial status register31 Bit Initial value Read/Write 7 1 R/(W) * H'9C 5 0 * SCI3 1 0 R 0 0 R/W 6 0 R/(W) 4 FER31 0 * 3 0 * 2 1 * TDRE31 RDRF31 OER31 R/(W) PER31 TEND31 MPBR31 MPBT31 R/(W) R R/(W) Multiprocessor bit transfer 0 1 A 0 multiprocessor bit is transmitted A 1 multiprocessor bit is transmitted Multiprocessor bit receive 0 1 0 Data in which the multiprocessor bit is 0 has been received Data in which the multiprocessor bit is 1 has been received Transmission in progress [Clearing conditions] * After reading TDRE31 = 1, cleared by writing 0 to TDRE * When data is written to TDR31 by an instruction Transmission ended [Setting conditions] * When bit TE in serial control register 31 (SCR31) is cleared to 0 * When bit TDRE31 is set to 1 when the last bit of a transmit character is sent Transmit end 1 Parity error 0 1 Reception in progress or completed normally [Clearing conditions] After reading PER31 = 1, cleared by writing 0 to PER31 A parity error has occurred during reception [Setting conditions] When the number of 1 bits in the receive data plus parity bit does not match the parity designated by the parity mode bit (PM31) in the serial mode register (SMR31) Reception in progress or completed normally [Clearing conditions] After reading FER31 = 1, cleared by writing 0 to FER31 A framing error has occurred during reception [Setting conditions] When the stop bit at the end of the receive data is checked for a value of 1 at completion of reception, and the stop bit is 0 Reception in progress or completed [Clearing conditions] After reading OER31 = 1, cleared by writing 0 to OER31 An overrun error has occurred during reception [Setting conditions] When the next serial reception is completed with RDRF31 set to 1 Framing error 0 1 Overrun error 0 1 Receive data register full 0 There is no receive data in RDR31 [Clearing conditions] * After reading RDRF31 = 1, cleared by writing 0 to RDRF31 * When RDR31 data is read by an instruction There is receive data in RDR31 [Setting conditions] When reception ends normally and receive data is transferred from RSR31 to RDR31 1 Transmit data register empty 0 Transmit data written in TDR31 has not been transferred to TSR31 [Clearing conditions] * After reading TDRE31 = 1, cleared by writing 0 to TDRE31 * When data is written to TDR31 by an instruction Transmit data has not been written to TDR31, or transmit data written in TDR31 has been transferred to TSR31 [Setting conditions] * When bit TE in serial control register 31 (SCR31) is cleared to 0 * When data is transferred from TDR31 to TSR31 1 Note: * Only a write of 0 for flag clearing is possible. 433 RDR31--Receive data register 31 Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R H'F9D 2 0 R 1 0 R SCI31 0 0 R RDR317 RDR316 RDR315 RDR314 RDR313 RDR312 RDR311 RDR310 Serial receive data 434 SCR1--Serial control register 1 Bit Initial value Read/Write 7 SNC1 0 R/W 6 SNC0 0 R/W 5 MRKON 0 R/W 4 LTCH 0 R/W 3 CKS3 0 R/W H'A0 2 CKS2 0 R/W 1 CKS1 0 R/W 0 SCI1 CKS0 0 R/W Clock select 2 to 0 Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 Prescaler Division Ratio o/1024 o/256 o/64 o/32 o/16 o/8 o/4 oW/4 Serial Clock Cycle Clock Cycle o = 2.5 MHz 409.6 s 102.4 s 25.6 s 12.8 s 6.4 s 3.2 s 1.6 s 50 s or 104.2 s Clock source select 0 Clock source is prescaler S, SCK1 is output 1 Clock source is external clock, SCK1 is input LATCH TAIL select 0 HOLD TAIL is output 1 LATCH TAIL is output Tail mark control 0 Tail mark is not output (synchronous mode) 1 Tail mark is output (SSB mode) Operating mode select 0 0 8-bit synchronous mode 1 16-bit synchronous mode 1 0 Continuous clock output mode 1 Reserved 435 SCSR1--Serial control status register 1 Bit Initial value Read/Write 7 -- 1 -- 6 SOL 0 R/W 5 ORER 0 R/(W)* 4 -- 1 -- 3 -- 1 -- H'A1 2 -- 1 -- 1 MTRF 0 R 0 SCI1 STF 0 R/W Start flag 0 Read Write 1 Read Write Transfer operation stopped Invalid Transfer operation in progress Starts transfer operation Tail mark transmission flag 0 Idle state, or 8-bit/16-bit data transfer in progress 1 Tail mark transmission in progress Overrun error flag 0 Clearing conditions: After reading ORER = 1, cleared by writing 0 to ORER 1 Setting conditions: When an external clock is used and the clock is input after transfer is completed Extension data bit 0 Read SO1 output level is low Write Changes SO1 output to low level 1 Read SO1 output level is high Write Changes SO1 output to high level Note: * Only a write of 0 for flag clearing is possible. 436 SDRU--Serial data register U Bit Initial value Read/Write 7 SDRU7 R/W 6 SDRU6 R/W 5 SDRU5 R/W 4 SDRU4 R/W 3 SDRU3 R/W H'A2 2 SDRU2 R/W 1 SDRU1 R/W 0 SCI1 SDRU0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Used for transmit data setting and receive data storage 8-bit transfer mode: Not used 16-bit transfer mode: Upper 8 bits of data register SDRL--Serial data register L Bit Initial value Read/Write 7 SDRL7 R/W 6 SDRL6 R/W 5 SDRL5 R/W 4 SDRL4 R/W 3 SDRL3 R/W H'A3 2 SDRL2 R/W 1 SDRL1 R/W SCI1 0 SDRL0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Used for transmit data setting and receive data storage 8-bit transfer mode: Data register 16-bit transfer mode: Lower 8 bits of data register 437 SMR32--Serial mode register 32 Bit Initial value Read/Write 7 COM32 0 R/W 6 CHR32 0 R/W 5 PE32 0 R/W 4 PM32 0 R/W 3 STOP32 0 R/W H'A8 2 MP32 0 R/W 1 0 R/W 0 0 SCI32 CKS321 CKS320 R/W Clock select 0 0 o clock 0 1 ow/2 clock/ow clock 1 0 o/16 clock 1 1 o/64 clock Multiprocessor mode 0 Multiprocessor communication function disabled 1 Multiprocessor communication function enabled Stop bit length 0 1 stop bit 1 2 stop bits Parity mode 0 Even parity 1 Odd parity Parity enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled Character length 0 8-bit data/5-bit data 1 7-bit data/5-bit data Communication mode 0 Asynchronous mode 1 Synchronous mode 438 BRR32--Bit rate register 32 Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'A9 2 1 R/W 1 1 R/W SCI32 0 1 R/W BRR327 BRR326 BRR325 BRR324 BRR323 BRR322 BRR321 BRR3120 Serial transmit/receive bit rate setting 439 SCR32--Serial control register 32 Bit Initial value Read/Write 7 TIE32 0 R/W 6 RIE32 0 R/W 5 TE32 0 R/W 4 RE32 0 R/W 3 0 R/W H'AA 2 0 R/W 1 0 R/W SCI32 0 0 R/W MPIE32 TEIE32 CKE321 CKE320 Clock enable Bit 0 Bit 1 CKE321 CKE320 Communication Mode Asynchronous 0 0 Synchronous Asynchronous 1 0 Synchronous Asynchronous 0 1 Synchronous Asynchronous 1 1 Synchronous Transmit end interrupt enable 0 1 Transmit end interrupt request (TEI) disabled Transmit end interrupt request (TEI) enabled Description Clock Source SCK 3 Pin Function I/O port Internal clock Serial clock output Internal clock Clock output Internal clock Reserved (Do not specify this combination) Clock input External clock Serial clock input External clock Reserved (Do not specify this combination) Reserved (Do not specify this combination) Multiprocessor interrupt enable 0 Multiprocessor interrupt request disabled (normal receive operation) [Clearing conditions] When data is received in which the multiprocessor bit is set to 1 Multiprocessor interrupt request enabled The receive interrupt request (RXI), receive error interrupt request (ERI), and setting of the RDRF, FER, and OER flags in the serial status register (SSR), are disabled until data with the multiprocessor bit set to 1 is received. 1 Receive enable 0 1 Receive operation disabled (RXD pin is I/O port) Receive operation enabled (RXD pin is receive data pin) Transmit enable 0 1 Transmit operation disabled (TXD pin is transmit data pin) Transmit operation enabled (TXD pin is transmit data pin) Receive interrupt enable 0 1 Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled Transmit interrupt enable 0 Transmit data empty interrupt request (TXI) disabled 1 Transmit data empty interrupt request (TXI) enabled 440 TDR32--Transmit data register 32 Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'AB 2 1 R/W 1 1 R/W SCI32 0 1 R/W TDR327 TDR326 TDR325 TDR324 TDR323 TDR322 TDR321 TDR320 Data for transfer to TSR 441 SSR32--Serial status register 32 Bit Initial value Read/Write 7 1 R/(W) * H'AC 5 0 4 FER32 0 * SCI32 1 0 R 0 0 R/W 6 0 R/(W) * 3 0 * 2 1 * TDRE32 RDRF32 OER32 R/(W) PER32 TEND32 MPBR32 MPBT32 R/(W) R R/(W) Multiprocessor bit transfer 0 1 A 0 multiprocessor bit is transmitted A 1 multiprocessor bit is transmitted Multiprocessor bit receive 0 1 0 Data in which the multiprocessor bit is 0 has been received Data in which the multiprocessor bit is 1 has been received Transmission in progress [Clearing conditions] * After reading TDRE32 = 1, cleared by writing 0 to TDRE32 * When data is written to TDR32 by an instruction Transmission ended [Setting conditions] * When bit TE in serial control register 32 (SCR32) is cleared to 0 * When bit TDRE32 is set to 1 when the last bit of a transmit character is sent Transmit end 1 Parity error 0 1 Reception in progress or completed normally [Clearing conditions] After reading PER32 = 1, cleared by writing 0 to PER32 A parity error has occurred during reception [Setting conditions] When the number of 1 bits in the receive data plus parity bit does not match the parity designated by the parity mode bit (PM32) in the serial mode register (SMR32) Reception in progress or completed normally [Clearing conditions] After reading FER32 = 1, cleared by writing 0 to FER32 A framing error has occurred during reception [Setting conditions] When the stop bit at the end of the receive data is checked for a value of 1 at completion of reception, and the stop bit is 0 Reception in progress or completed [Clearing conditions] After reading OER32 = 1, cleared by writing 0 to OER32 An overrun error has occurred during reception [Setting conditions] When the next serial reception is completed with RDRF32 set to 1 Framing error 0 1 Overrun error 0 1 Receive data register full 0 There is no receive data in RDR32 [Clearing conditions] * After reading RDRF32 = 1, cleared by writing 0 to RDRF32 * When RDR32 data is read by an instruction There is receive data in RDR32 [Setting conditions] When reception ends normally and receive data is transferred from RSR32 to RDR32 1 Transmit data register empty 0 Transmit data written in TDR32 has not been transferred to TSR32 [Clearing conditions] * After reading TDRE32 = 1, cleared by writing 0 to TDRE32 * When data is written to TDR32 by an instruction Transmit data has not been written to TDR32, or transmit data written in TDR32 has been transferred to TSR32 [Setting conditions] * When bit TE32 in serial control register 32 (SCR32) is cleared to 0 * When data is transferred from TDR32 to TSR32 1 Note: * Only a write of 0 for flag clearing is possible. 442 RDR32--Receive data register 32 Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R H'AD 2 0 R 1 0 R SCI32 0 0 R RDR327 RDR326 RDR325 RDR324 RDR323 RDR322 RDR321 RDR320 Serial receive data TMA--Timer mode register A Bit Initial value Read/Write 7 TMA7 0 R/W 6 TMA6 0 R/W 5 TMA5 0 R/W 4 -- 1 -- 3 TMA3 0 R/W H'B0 2 TMA2 0 R/W 1 TMA1 0 R/W Timer A 0 TMA0 0 R/W Clock output select* Internal clock select 0 0 0 o/32 Prescaler and Divider Ratio TMA3 TMA2 TMA1 TMA0 or Overflow Period 0 0 1 o/16 0 0 0 0 PSS o/8192 0 1 0 o/8 0 0 1 0 PSS o/4096 0 1 1 o/4 0 0 0 PSS o/2048 1 1 0 0 o W /32 0 0 1 1 PSS o/512 1 0 1 o W /16 1 0 0 0 o/256 PSS 1 1 0 o W /8 1 0 1 0 o/128 PSS 1 1 1 o W /4 1 1 0 o/32 PSS 0 Note: * Values when 1 1 1 o/8 PSS 0 bit CWOS = 0 in CWOSR. 0 0 0 oW/32768 1 PSW When bit 1 0 0 PSW oW/16384 1 CWOS = 1, oW/8192 0 0 PSW 1 1 ow is output oW/1024 0 1 1 PSW 1 regardless of the value of 1 1 0 0 PSW and TCA are reset bits TMA7 to 1 1 0 1 TMA5. 1 1 1 0 1 1 1 1 Function Interval timer Time base (overflow period) 443 TCA--Timer counter A Bit Initial value Read/Write 7 TCA7 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R H'B1 2 TCA2 0 R 1 TCA1 0 R Timer A 0 TCA0 0 R Count value 444 TCSRW--Timer control/status register W Bit Initial value Read/Write 7 B6WI 1 R 6 TCWE 0 R/(W)* 5 B4WI 1 R 4 TCSRWE 0 R/(W)* 3 B2WI 1 R H'B2 2 WDON 0 R/(W) * Watchdog timer 1 B0WI 1 R 0 WRST 0 R/(W) * Watchdog timer reset 0 [Clearing conditions] * Reset by RES pin * When TCSRWE = 1, and 0 is written in both B0WI and WRST 1 [Setting condition] When TCW overflows and a reset signal is generated Bit 0 write inhibit 0 Bit 0 is write-enabled 1 Bit 0 is write-protected Watchdog timer on 0 Watchdog timer operation is disabled 1 Watchdog timer operation is enabled Bit 2 write inhibit 0 Bit 2 is write-enabled 1 Bit 2 is write-protected Timer control/status register W write enable 0 Data cannot be written to bits 2 and 0 1 Data can be written to bits 2 and 0 Bit 4 write inhibit 0 Bit 4 is write-enabled 1 Bit 4 is write-protected Timer counter W write enable 0 Data cannot be written to TCW 1 Data can be written to TCW Bit 6 write inhibit 0 Bit 6 is write-enabled 1 Bit 6 is write-protected Note: * Write is permitted only under certain conditions. 445 TCW--Timer counter W Bit Initial value Read/Write 7 TCW7 0 R/W 6 TCW6 0 R/W 5 TCW5 0 R/W 4 TCW4 0 R/W 3 TCW3 0 R/W H'B3 2 TCW2 0 R/W Watchdog timer 1 TCW1 0 R/W 0 TCW0 0 R/W Count value TMC--Timer mode register C Bit Initial value Read/Write 7 TMC7 0 R/W 6 TMC6 0 R/W 5 TMC5 0 R/W 4 -- 1 -- 3 -- 1 -- H'B4 2 TMC2 0 R/W 1 TMC1 0 R/W Timer C 0 TMC0 0 R/W Clock select 0 0 0 Internal clock: o/8192 0 0 1 Internal clock: o/2048 0 1 0 Internal clock: o/512 0 1 1 Internal clock: o/64 1 0 0 Internal clock: o/16 1 0 1 Internal clock: o/4 1 1 0 Internal clock: ow/4 External event (TMIC): Counting 111 on rising or falling edge Counter up/down control 0 0 TCC is an up-counter 0 1 TCC is a down-counter 1* Hardware control of TCC up/down operation by UD pin input UD pin input high: Down-counter UD pin input low: Up-counter * Don't care Auto-reload function select 0 Interval timer function selected 1 Auto-reload function selected 446 TCC--Timer counter C Bit Initial value Read/Write 7 TCC7 0 R 6 TCC6 0 R 5 TCC5 0 R 4 TCC4 0 R 3 TCC3 0 R H'B5 2 TCC2 0 R 1 TCC1 0 R Timer C 0 TCC0 0 R Count value TLC--Timer load register C Bit Initial value Read/Write 7 TLC7 0 R/W 6 TLC6 0 R/W 5 TLC5 0 R/W 4 TLC4 0 R/W 3 TLC3 0 R/W H'B5 2 TLC2 0 R/W 1 TLC1 0 R/W Timer C 0 TLC0 0 R/W Reload value Note: TLC is allocated to the same address as TCC. In a write, the value is written to TLC. 447 TCRF--Timer control register F Bit Initial value Read/Write 7 TOLH 0 W 6 CKSH2 0 W 5 CKSH1 0 W 4 CKSH0 0 W 3 TOLL 0 W H'B6 2 CKSL2 0 W 1 CKSL1 0 W Timer F 0 CKSL0 0 W Clock select L 0 0 0 1 1 1 1 Toggle output level L 0 1 Clock select H 0 0 0 1 1 1 1 Toggle output level H 0 1 Low level High level 0 1 1 0 0 1 1 * 0 1 0 1 0 1 16-bit mode, counting on TCFL overflow signal Not available Internal clock o/32 Internal clock o/16 Internal clock o/4 Internal clock ow/4 * Don't care Low level High level 0 1 1 0 0 1 1 * 0 1 0 1 0 1 Counting on external event (TMIF) rising/falling edge Not available Internal clock o/32 Internal clock o/16 Internal clock o/4 Internal clock ow/4 * Don't care 448 TCSRF--Timer control/status register F Bit Initial value Read/Write 7 OVFH 0 R/(W)* 6 CMFH 0 R/(W)* 5 OVIEH 0 R/W 4 CCLRH 0 R/W 3 OVFL 0 R/(W)* H'B7 2 CMFL 0 R/(W)* 1 OVIEL 0 R/W Timer F 0 CCLRL 0 R/W Counter clear L 0 1 TCFL clearing by compare match is disabled TCFL clearing by compare match is enabled Timer overflow interrupt enable L 0 1 TCFL overflow interrupt request is disabled TCFL overflow interrupt request is enabled Compare match flag L 0 1 Clearing conditions: After reading CMFL = 1, cleared by writing 0 to CMFL Setting conditions: Set when the TCFL value matches the OCRFL value Timer overflow flag L 0 1 Clearing conditions: After reading OVFL = 1, cleared by writing 0 to OVFL Setting conditions: Set when TCFL overflows from H'FF to H'00 Counter clear H 0 1 16-bit mode: TCF clearing by compare match is disabled 8-bit mode: TCFH clearing by compare match is disabled 16-bit mode: TCF clearing by compare match is enabled 8-bit mode: TCFH clearing by compare match is enabled Timer overflow interrupt enable H 0 1 TCFH overflow interrupt request is disabled TCFH overflow interrupt request is enabled Compare match flag H 0 1 Clearing conditions: After reading CMFH = 1, cleared by writing 0 to CMFH Setting conditions: Set when the TCFH value matches the OCRFH value Timer overflow flag H 0 1 Clearing conditions: After reading OVFH = 1, cleared by writing 0 to OVFH Setting conditions: Set when TCFH overflows from H'FF to H'00 Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing. 449 TCFH--8-bit timer counter FH Bit Initial value Read/Write 7 TCFH7 0 R/W 6 TCFH6 0 R/W 5 TCFH5 0 R/W 4 TCFH4 0 R/W 3 TCFH3 0 R/W H'B8 2 TCFH2 0 R/W 1 TCFH1 0 R/W Timer F 0 TCFH0 0 R/W Count value Note: TCFH and TCFL can also be used as the upper and lower halves, respectively, of a 16-bit timer counter (TCF). TCFL--8-bit timer counter FL Bit Initial value Read/Write 7 TCFL7 0 R/W 6 TCFL6 0 R/W 5 TCFL5 0 R/W 4 TCFL4 0 R/W 3 TCFL3 0 R/W H'B9 2 TCFL2 0 R/W 1 TCFL1 0 R/W Timer F 0 TCFL0 0 R/W Count value Note: TCFH and TCFL can also be used as the upper and lower halves, respectively, of a 16-bit timer counter (TCF). OCRFH--Output compare register FH Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'BA 2 1 R/W 1 1 R/W Timer F 0 1 R/W OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0 Note: OCRFH and OCRFL can also be used as the upper and lower halves, respectively, of a 16-bit output compare register (OCRF). 450 OCRFL--Output compare register FL Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'BB 2 1 R/W 1 1 R/W Timer F 0 1 R/W OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 Note: OCRFH and OCRFL can also be used as the upper and lower halves, respectively, of a 16-bit output compare register (OCRF). 451 TMG--Timer mode register G Bit Initial value Read/Write 7 OVFH 0 R/(W)* 6 OVFL 0 R/(W)* 5 OVIE 0 W 4 IIEGS 0 W 3 CCLR1 0 W 2 CCLR0 0 W H'BC 1 CKS1 0 W 0 CKS0 0 W Timer G Clock select 00 01 10 11 Internal clock: counting on o/64 Internal clock: counting on o/32 Internal clock: counting on o/2 Internal clock: counting on ow/4 Counter clear 0 0 TCG clearing is disabled 0 1 TCG cleared by falling edge of input capture input signal 1 0 TCG cleared by rising edge of input capture input signal 1 1 TCG cleared by both edges of input capture input signal Input capture interrupt edge select 0 Interrupt generated on rising edge of input capture input signal 1 Interrupt generated on falling edge of input capture input signal Timer overflow interrupt enable 0 TCG overflow interrupt request is disabled 1 TCG overflow interrupt request is enabled Timer overflow flag L 0 Clearing conditions: After reading OVFL = 1, cleared by writing 0 to OVFL 1 Setting conditions: Set when TCG overflows from H'FF to H'00 Timer overflow flag H 0 Clearing conditions: After reading OVFH = 1, cleared by writing 0 to OVFH 1 Setting conditions: Set when TCG overflows from H'FF to H'00 Note: * Bits 7 and 6 can only be written with 0, for flag clearing. 452 ICRGF--Input capture register GF Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R H'BD 2 0 R 1 0 R Timer G 0 0 R ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0 Store TCG value at falling edge of input capture signal ICRGR--Input capture register GR Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R H'BE 2 0 R 1 0 R Timer G 0 0 R ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0 Store TCG value at rising edge of input capture signal 453 AMR--A/D mode register Bit Initial value Read/Write 7 CKS 0 R/W 6 TRGE 0 R/W 5 -- 1 -- 4 -- 1 -- 3 CH3 0 R/W H'C6 2 CH2 0 R/W A/D converter 1 CH1 0 R/W 0 CH0 0 R/W Channel select Bit 3 Bit 2 Bit 1 CH3 CH2 CH1 0 0 * 0 0 1 0 0 1 0 1 1 1 0 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 * External trigger select Bit 0 CH0 * 0 1 0 1 0 1 0 1 * Analog Input Channel No channel selected AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 Reserved * Don't care 0 Disables start of A/D conversion by external trigger 1 Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG Clock select Bit 7 CKS Conversion Period 0 62/o 1 31/o Conversion Time o = 1 MHz o = 5 MHz 62 s 31 s 12.4 s --* Note: * Operation is not guaranteed with a conversion time of less than 12.4 s Select a setting that gives a conversion time of at least 12.4 s. 454 ADRRH--A/D result register H ADRRL--A/D result register L ADRRH Bit Initial value Read/Write 7 ADR9 R 6 ADR8 R 5 ADR7 R 4 ADR6 R 3 ADR5 R H'C4 H'C5 A/D converter 2 ADR4 R 1 ADR3 R 0 ADR2 R Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A/D conversion result ADRRL Bit Initial value Read/Write 7 ADR1 R 6 ADR0 R 5 -- -- -- 4 -- -- -- 3 -- -- -- 2 -- -- -- 1 -- -- -- 0 -- -- -- Undefined Undefined A/D conversion result ADSR--A/D start register Bit Initial value Read/Write 7 ADSF 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- H'C7 2 -- 1 -- A/D converter 1 -- 1 -- 0 -- 1 -- A/D status flag 0 Read Indicates completion of A/D conversion Write Stops A/D conversion 1 Read Indicates A/D conversion in progress Write Starts A/D conversion 455 PMR1--Port mode register 1 Bit Initial value Read/Write 7 IRQ3 0 R/W 6 IRQ2 0 R/W 5 IRQ1 0 R/W 4 IRQ4 0 R/W 3 TMIG 0 R/W 2 TMOFH 0 R/W 1 TMOFL 0 R/W H'C8 0 TMOW 0 R/W I/O port P10/TMOW pin function switch 0 Functions as P10 I/O pin 1 Functions as TMOW output pin P11/TMOFL pin function switch 0 Functions as P11 I/O pin 1 Functions as TMOFL output pin P12/TMOFH pin function switch 0 Functions as P12 I/O pin 1 Functions as TMOFH output pin P13/TMIG pin function switch 0 Functions as P13 I/O pin 1 Functions as TMIG input pin P14/IRQ4/ADTRG pin function switch 0 Functions as P14 I/O pin 1 Functions as IRQ4/ADTRG input pin P15/IRQ1/TMIC pin function switch 0 Functions as P15 I/O pin 1 Functions as IRQ1/TMIC input pin P16/IRQ2 pin function switch 0 Functions as P16 I/O pin 1 Functions as IRQ2 input pin P17/IRQ3/TMIF pin function switch 0 Functions as P17 I/O pin 1 Functions as IRQ3/TMIF input pin 456 PMR2--Port mode register 2 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 POF1 0 R/W 4 -- 1 -- 3 -- 1 -- H'C9 2 SO1 0 R/W 1 SI1 0 R/W I/O port 0 SCK1 0 R/W P20/SCK1 function switch 0 Functions as P20 I/O 1 Functions as SCK1 I/O P21/SI1 function switch 0 Functions as P21 I/O 1 Functions as SI1 input P22/SO1 function switch 0 Functions as P22 I/O 1 Functions as SO1 output P22/SO1 function PMOS control 0 CMOS setting 1 NMOS open-drain setting 457 PMR3--Port mode register 3 Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 WDCKS 0 R/W 4 NCS 0 R/W 3 IRQ0 0 R/W 2 RESO 0 R/W H'CA 1 UD 0 R/W 0 -- 0 -- I/O port P31/UD pin function switch 0 Functions as P31 I/O pin 1 Functions as UD input pin P32/RESO pin function switch 0 Functions as P32 I/O pin 1 Functions as RESO I/O pin P43/IRQ0 pin function switch 0 Functions as P43 I/O pin 1 Functions as IRQ0 input pin TMIG noise canceler select 0 Noise cancellation function not used 1 Noise cancellation function used Watchdog timer switch 0 o8192 1 ow/4 PMR4--Port mode register 4 Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 0 R/W 3 0 R/W H'CB 2 0 R/W 1 0 R/W I/O port 0 0 R/W NMOD4 NMOD3 NMOD2 NMOD1 NMOD0 0 CMOS setting 1 NMOS open-drain setting (n = 4 to 0) Note: When the PCR2 specification is 1 (output port specification) 458 PMR5--Port mode register 5 Bit Initial value Read/Write 7 WKP7 0 R/W 6 WKP6 0 R/W 5 WKP5 0 R/W 4 WKP4 0 R/W 3 WKP3 0 R/W H'CC 2 WKP2 0 R/W 1 WKP1 0 R/W I/O port 0 WKP0 0 R/W P5n/WKPn pin function switch 0 Functions as P5n I/O pin 1 Functions as WKPn input pin (n = 7 to 0) PDR1--Port data register 1 Bit Initial value Read/Write 7 P17 0 R/W 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W 3 P1 3 0 R/W H'D4 2 P1 2 0 R/W 1 P11 0 R/W I/O ports 0 P10 0 R/W Data for port 1 pins PDR2--Port data register 2 Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 P24 0 R/W 3 P23 0 R/W H'D5 2 P22 0 R/W 1 P21 0 R/W I/O ports 0 P20 0 R/W Data for port 2 pins 459 PDR3--Port data register 3 Bit Initial value Read/Write 7 P3 7 0 R/W 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W 3 P33 0 R/W H'D6 2 P32 0 R/W 1 P31 0 R/W I/O ports 0 P30 0 R/W Data for port 3 pins PDR4--Port data register 4 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 P43 1 R H'D7 2 P42 0 R/W 1 P41 0 R/W I/O ports 0 P40 0 R/W Reads P43 state Data for port pins P42 to P40 PDR5--Port data register 5 Bit Initial value Read/Write 7 P5 7 0 R/W 6 P56 0 R/W 5 P55 0 R/W 4 P54 0 R/W 3 P53 0 R/W H'D8 2 P52 0 R/W 1 P51 0 R/W I/O ports 0 P50 0 R/W Data for port 5 pins 460 PDR6--Port data register 6 Bit Initial value Read/Write 7 P6 7 0 R/W 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W 3 P63 0 R/W H'D9 2 P62 0 R/W 1 P61 0 R/W I/O ports 0 P60 0 R/W Data for port 6 pins PDR7--Port data register 7 Bit Initial value Read/Write 7 P7 7 0 R/W 6 P76 0 R/W 5 P75 0 R/W 4 P74 0 R/W 3 P73 0 R/W H'DA 2 P72 0 R/W 1 P71 0 R/W I/O ports 0 P70 0 R/W Data for port 7 pins PDR8--Port data register 8 Bit Initial value Read/Write 7 P8 7 0 R/W 6 P86 0 R/W 5 P85 0 R/W 4 P84 0 R/W 3 P83 0 R/W H'DB 2 P82 0 R/W 1 P81 0 R/W I/O ports 0 P80 0 R/W Data for port 8 pins 461 PDR9--Port data register 9 Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 P93 0 R/W H'DC 2 P92 0 R/W 1 P91 0 R/W I/O ports 0 P90 0 R/W Data for port 9 pins PDRA--Port data register A Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PA3 0 R/W H'DD 2 PA2 0 R/W 1 PA1 0 R/W I/O ports 0 PA0 0 R/W Data for port A pins PDRB--Port data register B Bit 7 PB 7 Read/Write R 6 PB 6 R 5 PB 5 R 4 PB 4 R 3 PB 3 R H'DE 2 PB 2 R 1 PB 1 R I/O ports 0 PB 0 R Read port B pin states 462 PUCR1--Port pull-up control register 1 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'E0 2 0 R/W 1 0 R/W I/O ports 0 0 R/W PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10 Port 1 input pull-up MOS control 0 Input pull-up MOS is off 1 Input pull-up MOS is on Note: When the PCR1 specification is 0 (input port specification) PUCR3--Port pull-up control register 3 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'E1 2 0 R/W 1 0 R/W I/O ports 0 0 R/W PUCR3 7 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 PUCR30 Port 3 input pull-up MOS control 0 Input pull-up MOS is off 1 Input pull-up MOS is on Note: When the PCR3 specification is 0 (input port specification) 463 PUCR5--Port pull-up control register 5 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'E2 2 0 R/W 1 0 R/W I/O ports 0 0 R/W PUCR5 7 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 Port 5 input pull-up MOS control 0 Input pull-up MOS is off 1 Input pull-up MOS is on Note: When the PCR5 specification is 0 (input port specification) PUCR6--Port pull-up control register 6 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'E3 2 0 R/W 1 0 R/W I/O ports 0 0 R/W PUCR6 7 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60 Port 6 input pull-up MOS control 0 Input pull-up MOS is off 1 Input pull-up MOS is on Note: When the PCR6 specifications 0 (input port specification) PCR1--Port control register 1 Bit Initial value Read/Write 7 PCR17 0 W 6 PCR16 0 W 5 PCR15 0 W 4 PCR14 0 W 3 PCR13 0 W H'E4 2 PCR1 2 0 W 1 PCR11 0 W I/O ports 0 PCR10 0 W Port 1 input/output select 0 Input pin 1 Output pin 464 PCR2--Port control register 2 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 PCR24 0 W 3 PCR23 0 W H'E5 2 PCR22 0 W 1 PCR21 0 W I/O ports 0 PCR20 0 W Port 2 input/output select 0 Input pin 1 Output pin PCR3--Port control register 3 Bit Initial value Read/Write 7 PCR3 7 0 W 6 PCR3 6 0 W 5 PCR3 5 0 W 4 PCR3 4 0 W 3 PCR3 3 0 W H'E6 2 PCR32 0 W 1 PCR31 0 W I/O ports 0 PCR30 0 W Port 3 input/output select 0 Input pin 1 Output pin PCR4--Port control register 4 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- H'E7 2 PCR42 0 W 1 PCR41 0 W I/O ports 0 PCR40 0 W Port 4 input/output select 0 Input pin 1 Output pin 465 PCR5--Port control register 5 Bit Initial value Read/Write 7 PCR57 0 W 6 PCR56 0 W 5 PCR55 0 W 4 PCR54 0 W 3 PCR53 0 W H'E8 2 PCR52 0 W 1 PCR51 0 W I/O ports 0 PCR50 0 W Port 5 input/output select 0 Input pin 1 Output pin PCR6--Port control register 6 Bit Initial value Read/Write 7 PCR6 7 0 W 6 PCR6 6 0 W 5 PCR6 5 0 W 4 PCR6 4 0 W 3 PCR6 3 0 W H'E9 2 PCR6 2 0 W 1 PCR6 1 0 W I/O ports 0 PCR6 0 0 W Port 6 input/output select 0 Input pin 1 Output pin PCR7--Port control register 7 Bit Initial value Read/Write 7 PCR77 0 W 6 PCR76 0 W 5 PCR75 0 W 4 PCR74 0 W 3 PCR73 0 W H'EA 2 PCR72 0 W 1 PCR71 0 W I/O ports 0 PCR70 0 W Port 7 input/output select 0 Input pin 1 Output pin 466 PCR8--Port control register 8 Bit Initial value Read/Write 7 PCR87 0 W 6 PCR86 0 W 5 PCR85 0 W 4 PCR84 0 W 3 PCR83 0 W H'EB 2 PCR82 0 W 1 PCR81 0 W I/O ports 0 PCR80 0 W Port 8 input/output select 0 Input pin 1 Output pin PCR9--Port control register 9 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PCR93 0 W H'EC 2 PCR92 0 W 1 PCR91 0 W I/O ports 0 PCR90 0 W Port 9 input/output select 0 Input pin 1 Output pin PCRA--Port control register A Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 PCRA 3 0 W H'ED 2 PCRA 2 0 W 1 0 W I/O ports 0 0 W PCRA 1 PCRA 0 Port A input/output select 0 Input pin 1 Output pin 467 SYSCR1--System control register 1 Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 LSON 0 R/W H'F0 2 -- 1 -- System control 1 MA1 1 R/W 0 MA0 1 R/W Active (medium-speed) mode clock select 0 0 oosc /16 1 oosc /32 1 0 oosc /64 1 o osc /128 Low speed on flag 0 The CPU operates on the system clock (o) 1 The CPU operates on the subclock (oSUB ) Standby timer select 2 to 0 0 0 0 Wait time = 8,192 states 1 Wait time = 16,384 states 1 0 Wait time = 1,024 states 1 Wait time = 2,048 states 1 0 0 Wait time = 4,096 states 1 Wait time = 2 states 1 0 Wait time = 8 states 1 Wait time = 16 states Software standby 0 * When a SLEEP instruction is executed in active mode, a transition is made to sleep mode * When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode 1 * When a SLEEP instruction is executed in active mode, a transition is made to standby mode or watch mode * When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode 468 SYSCR2--System control register 2 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 NESEL 1 R/W 3 DTON 0 R/W H'F1 2 MSON 0 R/W System control 1 SA1 0 R/W 0 SA0 0 R/W Subactive mode clock select 0 0 o W /8 1 o W /4 1 * o W /2 *: Don't care Medium speed on flag 0 Operates in active (high-speed) mode 1 Operates in active (medium-speed) mode Direct transfer on flag 0 * When a SLEEP instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode * When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode 1 * When a SLEEP instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1 * When a SLEEP instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1 * When a SLEEP instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 1 Noise elimination sampling frequency select 0 Sampling rate is oOSC /16 1 Sampling rate is oOSC /4 469 IEGR--IRQ edge select register Bit Initial value Read/Write 7 -- 0 -- 6 -- 1 -- 5 -- 1 -- 4 IEG4 0 R/W 3 IEG3 0 R/W H'F2 2 IEG2 0 R/W 1 IEG1 0 R/W System control 0 IEG0 0 R/W IRQ0 edge select 0 Falling edge of IRQ0 signal input is detected 1 Rising edge of IRQ0 signal input is detected IRQ1 edge select 0 Falling edge of IRQ1, TMIC pin input is detected 1 Rising edge of IRQ1, TMIC pin input is detected IRQ2 edge select 0 Falling edge of IRQ2 pin input is detected 1 Rising edge of IRQ2 pin input is detected IRQ3 edge select 0 Falling edge of IRQ3, TMIF pin input is detected 1 Rising edge of IRQ3, TMIF pin input is detected IRQ4 edge select 0 Falling edge of IRQ4 pin and ADTRG pin is detected 1 Rising edge of IRQ4 pin and ADTRG pin is detected 470 IENR1--Interrupt enable register 1 Bit Initial value Read/Write 7 IENTA 0 R/W 6 IENS1 0 R/W 5 IENWP 0 R/W 4 IEN4 0 R/W 3 IEN3 0 R/W H'F3 2 IEN2 0 R/W 1 System control 0 IEN0 0 R/W IEN1 0 R/W IRQ4 to IRQ0 interrupt enable 0 Disables IRQ4 to IRQ0 interrupt requests 1 Enables IRQ4 to IRQ0 interrupt requests Note: IRQ0 is an internal signal that performs interfacing to the FLEXTM decoder incorporated in the chip. Wakeup interrupt enable 0 Disables WKP7 to WKP0 interrupt requests 1 Enables WKP7 to WKP0 interrupt requests SCI1 interrupt enable 0 Disables SCI1 interrupt requests 1 Enables SCI1 interrupt requests Note: SCI1 is an internal function that performs interfacing to the FLEXTM decoder incorporated in the chip. Timer A interrupt enable 0 Disables timer A interrupt requests 1 Enables timer A interrupt requests 471 IENR2--Interrupt enable register 2 Bit Initial value Read/Write 7 IENDT 0 R/W 6 IENAD 0 R/W 5 -- 0 R/W 4 IENTG 0 R/W 3 0 R/W H'F4 2 0 R/W System control 1 IENTC 0 R/W 0 -- 0 -- IENTFH IENTFL Timer C interrupt enable Disables timer C interrupt requests 0 Enables timer C interrupt requests 1 Timer FL interrupt enable 0 Disables timer FL interrupt requests 1 Enables timer FL interrupt requests Timer FH interrupt enable 0 Disables timer FH interrupt requests 1 Enables timer FH interrupt requests Timer G interrupt enable 0 Disables timer G interrupt requests 1 Enables timer G interrupt requests A/D converter interrupt enable 0 Disables A/D converter interrupt requests 1 Enables A/D converter interrupt requests Direct transition interrupt enable 0 Disables direct transition interrupt requests 1 Enables direct transition interrupt requests 472 IRR1--Interrupt request register 1 Bit Initial value Read/Write 7 IRRTA 0 R/(W)* 6 IRRS1 0 R/(W)* 5 -- 1 -- 4 IRRI4 0 R/(W)* 3 IRRI3 0 R/(W)* H'F6 2 IRRI2 0 R/(W)* 1 System control 0 IRRI0 0 R/(W)* IRRI1 0 R/(W)* IRQ4 to IRQ0 interrupt request flags 0 Clearing conditions: When IRRIn = 1, it is cleared by writing 0 1 Setting conditions: When pin IRQn is designated for interrupt input and the designated signal edge is input (n = 4 to 0) Note: IRQ0 is an internal signal that performs interfacing to the FLEXTM decoder incorporated in the chip. SCI1 interrupt request flag 0 Clearing conditions: When IRRS1 = 1, it is cleared by writing 0 1 Setting conditions: When SCI1 completes transfer Note: SCI1 is an internal function that performs interfacing to the FLEXTM decoder incorporated in the chip. Timer A interrupt request flag 0 Clearing conditions: When IRRTA = 1, it is cleared by writing 0 1 Setting conditions: When the timer A counter value overflows (rom H'FF to H'00) Note: * Bits 7, 6, and 4 to 0 can only be written with 0, for flag clearing. 473 IRR2--Interrupt request register 2 Bit Initial value Read/Write 7 IRRDT 0 R/(W)* 6 IRRAD 0 R/(W)* 5 -- 0 R/W 4 IRRTG 0 R/(W)* 3 0 R/(W)* 2 0 R/(W)* H'F7 1 IRRTC 0 R/(W)* 0 -- 0 -- System control IRRTFH IRRTFL Timer C interrupt request flag 0 Clearing conditions: When IRRTC = 1, it is cleared by writing 0 1 Setting conditions: When the timer C counter value overflows (from H'FF to H'00) or underflows (from H'00 to H'FF) Timer FL interrupt request flag 0 Clearing conditions: When IRRTFL = 1, it is cleared by writing 0 1 Setting conditions: When counter FL and output compare register FL match in 8-bit timer mode Timer FH interrupt request flag 0 Clearing conditions: When IRRTFH = 1, it is cleared by writing 0 1 Setting conditions: When counter FH and output compare register FH match in 8-bit timer mode, or when 16-bit counters FL and FH and output compare registers FL and FH match in 16-bit timer mode Timer G interrupt request flag 0 Clearing conditions: When IRRTG = 1, it is cleared by writing 0 1 Setting conditions: When the TMIG pin is designated for TMIG input and the designated signal edge is input A/D converter interrupt request flag 0 Clearing conditions: When IRRAD = 1, it is cleared by writing 0 1 Setting conditions: When the A/D converter completes conversion and ADSF is reset Direct transition interrupt request flag 0 Clearing conditions: When IRRDT = 1, it is cleared by writing 0 1 Setting conditions: When a SLEEP instruction is executed while DTON is set to 1, and a direct transition is made Note: * Bits 7, 6 and 4 to 1 can only be written with 0, for flag clearing. 474 IWPR--Wakeup interrupt request register Bit Initial value Read/Write 7 IWPF7 0 R/(W)* 6 IWPF6 0 R/(W)* 5 IWPF5 0 R/(W)* 4 IWPF4 0 R/(W)* 3 IWPF3 0 R/(W)* H'F9 2 IWPF2 0 R/(W)* System control 1 IWPF1 0 R/(W)* 0 IWPF0 0 R/(W)* Wakeup interrupt request register 0 Clearing conditions: When IWPFn = 1, it is cleared by writing 0 1 Setting conditions: When pin WKPn is designated for wakeup input and a rising or falling edge is input at that pin (n = 7 to 0) Note: * All bits can only be written with 0, for flag clearing. 475 CKSTPR1--Clock stop register 1 Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'FA 2 1 R/W System control 1 1 R/W 0 1 R/W S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Timer A module standby mode control 0 Timer A is set to module standby mode 1 Timer A module standby mode is cleared Timer C module standby mode control 0 Timer C is set to module standby mode 1 Timer C module standby mode is cleared Timer F module standby mode control 0 Timer F is set to module standby mode 1 Timer F module standby mode is cleared Timer G interrupt enable 0 Timer G is set to module standby mode 1 Timer G module standby mode is cleared A/D converter module standby mode control 0 A/D converter is set to module standby mode 1 A/D converter module standby mode is cleared SCI32 module standby mode control 0 SCI32 is set to module standby mode 1 SCI32 module standby mode is cleared SCI31 module standby mode control 0 SCI31 is set to module standby mode 1 SCI31 module standby mode is cleared SCI1 module standby mode control 0 SCI1 is set to module standby mode 1 SCI1 module standby mode is cleared 476 CKSTPR2--Clock stop register 2 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- H'FB 2 WDCKSTP System control 1 -- 1 -- 0 -- 1 -- 1 R/W WDT module standby mode control 0 WDT is set to module standby mode 1 WDT module standby mode is cleared 477 Appendix C I/O Port Block Diagrams C.1 Block Diagrams of Port 1 SBY (low level during reset and in standby mode) VCC VCC PMR1n Internal data bus IRQn-4 PUCR1n P1n PDR1n VSS PCR1n PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 n = 7 to 4 Figure C-1 (a) Port 1 Block Diagram (Pins P17 to P14) 478 SBY PUCR13 VCC VCC Internal data bus PMR13 P13 PDR13 VSS PCR13 Timer G module TMIG PDR1 PCR1 PMR1 PUCR1 : Port data register 1 : Port control register 1 : Port mode register 1 : Port pull-up control register 1 Figure C-1 (b) Port 1 Block Diagram (Pin P13) 479 Timer F module SBY TMOFH (P12) TMOFL (P11) PUCR1n VCC Internal data bus VCC PMR1n P1n PDR1n VSS PCR1n PDR1: PCR1: PMR1: PUCR1: n= 2 or 1 Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C-1 (c) Port 1 Block Diagram (Pins P12 and P11) 480 ow Timer A module TMOW SBY CWOS PUCR10 VCC VCC PMR10 Internal data bus P10 PDR10 VSS PCR10 PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C-1 (d) Port 1 Block Diagram (Pin P10) 481 C.2 Block Diagrams of Port 2 [Chip Internal I/O Port] RES (Low in reset) FLEXTM Decoder RESET PDR24 Internal data bus Internal data bus PCR24 PDR2: Port data register 2 PCR2: Port control register 2 Figure C-2 (a) Port 2 Block Diagram (Pin P24) FLEXTM Decoder SS RES PDR23 PCR23 PDR2: Port data register 2 PCR2: Port control register 2 Figure C-2 (b) Port 2 Block Diagram (Pin P23) 482 SCI1 module SO1 RES FLEXTM Decoder PMR22 MOSI PDR22 PCR22 PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 Figure C-2 (c) Port 2 Block Diagram (Pin P22) Internal data bus 483 PMR21 FLEXTM Decoder Internal data bus SCI1 module PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 SI1 MISO PDR21 PCR21 RES Figure C-2 (d) Port 2 Block Diagram (Pin P21) 484 SCI1 module EXCK SCK0 SCK1 RES FLEXTM Decoder PMR20 SCK PDR20 PCR20 PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 Figure C-2 (e) Port 2 Block Diagram (Pin P20) Internal data bus 485 C.3 Block Diagrams of Port 3 SBY PUCR3n VCC VCC Internal data bus P3n PDR3n VSS PCR3n PDR3: PCR3: PMR3: Port data register 3 Port control register 3 Port mode register 3 PUCR3: Port pull-up control register 3 n=7 or 6 Figure C-3 (a) Port 3 Block Diagram (Pins P37 and P36) 486 SBY PUCR35 SCINV1 VCC VCC SCI31 module TE31 TXD31 Internal data bus P35 PDR35 PCR35 VSS PDR3 PCR3 : Port data register 3 : Port control register 3 PUCR3 : Port pull-up control register 3 SCINV1 : Bit 1 of serial port control register (SPCR) Figure C.3 (b) Port 3 Block Diagram (Pin P35) 487 SBY PUCR34 VCC VCC SCI31 module RE31 RXD31 P34 PDR34 Internal data bus PCR34 VSS SCINV0 PDR3 PCR3 PUCR3 : Port data register 3 : Port control register 3 : Port pull-up control register 3 SCINV0 : Bit 0 of serial port control register (SPCR) Figure C.3 (c) Port 3 Block Diagram (Pin P34) 488 SBY PUCR33 SCI31 module VCC VCC SCKIE31 SCKOE31 SCKO31 SCKI31 P33 PDR33 Internal data bus PCR33 VSS PDR3 : Port data register 3 PCR3 : Port control register 3 PUCR3 : Port pull-up control register 3 Figure C.3 (d) Port 3 Block Diagram (Pin P33) 489 SBY RESO PUCR32 VCC PMR32 Internal data bus VCC P32 PDR32 VSS PCR32 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C.3 (e) Port 3 Block Diagram (Pin P32) 490 SBY PUCR31 VCC Internal data bus Timer C module UD VCC PMR31 P31 PDR31 VSS PCR31 PDR3: PCR3: PMR3: PUCR3: Port data register 3 Port control register 3 Port mode register 3 Port pull-up control register 3 Figure C-3 (f) Port 3 Block Diagram (Pin P31) 491 SBY PUCR30 VCC VCC Internal data bus P30 PDR30 VSS PCR30 PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 Figure C-3 (g) Port 3 Block Diagram (Pin P30) 492 C.4 Block Diagrams of Port 4 FLEXTM Decoder READY IRQ0 PMR4: Port mode register 4 RES Figure C.4 (a) Port 4 Block Diagram (Pin P4 3) [Chip Internal Input Port] Internal data bus PMR43 493 SBY SCINV3 VCC SCI32 module TE32 TXD32 P42 PDR42 Internal data bus PCR42 VSS PDR4 PCR4 : Port data register 4 : Port control register 4 SCINV3 : Bit 3 of serial port control register (SPCR) Figure C.4 (b) Port 4 Block Diagram (Pin P42) 494 SBY VCC SCI32 module RE32 RXD32 P41 PDR41 Internal data bus PCR41 VSS SCINV2 PDR4 PCR4 : Port data register 4 : Port control register 4 SCINV2 : Bit 2 of serial port control register (SPCR) Figure C.4 (c) Port 4 Block Diagram (Pin P41) 495 SBY SCI32 module VCC SCKIE32 SCKOE32 SCKO32 SCKI32 P40 PDR40 Internal data bus PCR40 VSS PDR4: Port data register 4 PCR4: Port control register 4 Figure C.4 (d) Port 4 Block Diagram (Pin P40) 496 C.5 Block Diagram of Port 5 SBY PUCR5n VCC VCC PMR5n Internal data bus P5n PDR5n VSS PCR5n WKPn PDR5: Port data register 5 PCR5: Port control register 5 PMR5: Port mode register 5 PUCR5: Port pull-up control register 5 n = 7 to 0 Figure C.5 Port 5 Block Diagram 497 C.6 Block Diagram of Port 6 SBY PUCR6n VCC VCC PDR6n PCR6n P6n VSS PDR6: Port data register 6 PCR6: Port control register 6 PUCR6: Port pull-up control register 6 n = 7 to 0 Figure C.6 Port 6 Block Diagram 498 Internal data bus C.7 Block Diagram of Port 7 SBY VCC Internal data bus PDR7n PCR7n P7n VSS PDR7: Port data register 7 PCR7: Port control register 7 n = 7 to 0 Figure C.7 Port 7 Block Diagram 499 C.8 Block Diagrams of Port 8 SBY PDR8n PCR8n P8n VSS PDR8: PCR8: n= 7 to 0 Port data register 8 Port control register 8 Figure C-8 Port 8 Block Diagram 500 Internal data bus VCC C.9 Block Diagram of Port 9 SBY VCC Internal data bus PDR9n PCR9n P9n VSS PDR9: Port data register 9 PCR9: Port control register 9 n = 3 to 0 Figure C-9 Port 9 Block Diagram 501 C.10 Block Diagram of Port A SBY VCC PDRAn Internal data bus PCRAn PAn VSS PDRA: Port data register A PCRA: Port control register A n = 3 to 0 Figure C.10 Port A Block Diagram 502 C.11 Block Diagram of Port B Internal data bus PBn A/D module DEC AMR3 to AMR0 VIN n = 7 to 0 Figure C-11 Port B Block Diagram 503 Appendix D Port States in the Different Processing States Table D-1 Port Port States Overview Reset Sleep Retained Retained Subsleep Retained Retained Standby Watch Subactive Functions Functions Active Functions Functions P17 to P10 Highimpedance P24 P23 Low High HighRetained impedance*1 Retained Retained P22 to P20 Low P37 to P30 HighRetained impedance*2 P43 High Retained Retained Retained HighRetained impedance*1 Retained Highimpedance Retained Retained Retained Retained Retained Retained Highimpedance Retained Retained Retained Retained Retained Retained Highimpedance HighRetained impedance*1 Highimpedance Highimpedance Highimpedance Highimpedance Highimpedance Highimpedance Retained Retained Retained Retained Retained Highimpedance Functions Functions Functions Functions Functions Functions Highimpedance Functions Functions Functions Functions Functions Functions Highimpedance Retained Functions Functions Functions Functions P42 to P40 Highimpedance P57 to P50 Highimpedance P67 to P60 Highimpedance P77 to P70 Highimpedance P87 to P80 Highimpedance P93 to P90 Highimpedance PA 3 to PA0 Highimpedance PB 7 to PB0 Highimpedance Notes: 1. High level output when MOS pull-up is in on state. 2. Reset output from P32 pin only. 504 Appendix E List of Product Codes Table E.1 Product Code Lineup Package Product Type H8/3937 Series H8/3936 H8/3935 Mask ROM versions Mask ROM versions H8/3937 Mask ROM versions ZTAT versions H8/3937R Series H8/3935R Mask ROM versions H8/3936R Mask ROM versions H8/3937R Mask ROM versions ZTAT versions Product Code HD6433935X HD6433935W HD6433936X HD6433936W HD6433937X HD6433937W HD6473937X HD6473937W HD6433935RX HD6433935RW HD6433936RX HD6433936RW HD6433937RX HD6433937RW HD6473937RX HD6473937RW Mark Code HD6433935(***)X HD6433935(***)W HD6433936(***)X HD6433936(***)W HD6433937(***)X HD6433937(***)W HD6473937X HD6473937W HD6433935R(***)X HD6433935R(***)W HD6433936R(***)X HD6433936R(***)W HD6433937R(***)X HD6433937R(***)W HD6473937RX HD6473937RW (Hitachi Package Code) 100-pin TQFP (TFP-100B) 100-pin TQFP (TFP-100G) 100-pin TQFP (TFP-100B) 100-pin TQFP (TFP-100G) 100-pin TQFP (TFP-100B) 100-pin TQFP (TFP-100G) 100-pin TQFP (TFP-100B) 100-pin TQFP (TFP-100G) 100-pin TQFP (TFP-100B) 100-pin TQFP (TFP-100G) 100-pin TQFP (TFP-100B) 100-pin TQFP (TFP-100G) 100-pin TQFP (TFP-100B) 100-pin TQFP (TFP-100G) 100-pin TQFP (TFP-100B) 100-pin TQFP (TFP-100G) Note: For mask ROM versions, (***) is the ROM code. 505 Appendix F Package Dimensions Dimensional drawings of the H8/3937 Series and H8/3937R Series packages TFP-100B and TFP100G are shown in following figures F-1 and F-2, respectively. Unit: mm 16.0 0.2 14 75 76 16.0 0.2 51 50 100 1 *0.22 0.05 0.20 0.04 25 0.08 M 26 *0.17 0.05 0.15 0.04 1.20 Max 1.00 0.5 1.0 1.0 0 - 8 0.5 0.1 0.10 0.10 0.10 *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) TFP-100B -- Conforms 0.5 g Figure F-1 TFP-100B Package Dimensions 506 14.0 0.2 12 75 76 14.0 0.2 51 50 0.4 Unit: mm 100 1 *0.18 0.05 0.16 0.04 25 0.07 M 26 1.2 *0.17 0.05 0.15 0.04 1.20 Max 1.00 1.0 0 - 8 0.5 0.1 0.10 0.10 0.10 *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) TFP-100G -- Conforms 0.4 g Figure F-2 TFP-100G Package Dimensions 507 508 H8/3937 Series, H8/3937R Series Hardware Manual Publication Date: 1st Edition, February 2001 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright (c) Hitachi, Ltd., 2001. All rights reserved. Printed in Japan. |
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